From miod@online.fr Wed Dec 24 06:57:18 2014 Delivered-To: david@gwynne.id.au Received: by 10.152.48.80 with SMTP id j16csp1451617lan; Tue, 23 Dec 2014 12:57:19 -0800 (PST) X-Received: by 10.236.23.38 with SMTP id u26mr8529811yhu.108.1419368238689; Tue, 23 Dec 2014 12:57:18 -0800 (PST) Return-Path: Received: from cvs.openbsd.org (cvs.openbsd.org. [199.185.137.3]) by mx.google.com with ESMTPS id d80si10826930ykd.123.2014.12.23.12.57.17 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 23 Dec 2014 12:57:18 -0800 (PST) Received-SPF: none (google.com: miod@online.fr does not designate permitted sender hosts) client-ip=199.185.137.3; Authentication-Results: mx.google.com; spf=none (google.com: miod@online.fr does not designate permitted sender hosts) smtp.mail=miod@online.fr Received: from shear.ucar.edu (lists.openbsd.org [192.43.244.163]); by cvs.openbsd.org (OpenSMTPD) with ESMTPS id 72c2102a; TLS version=TLSv1/SSLv3 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=FAIL; Tue, 23 Dec 2014 13:57:15 -0700 (MST) Received: from tazenat.gentiane.org (odyssee.gentiane.org [80.65.224.82]) by shear.ucar.edu (8.14.8/8.14.8) with ESMTP id sBNLAUYJ024211 (version=TLSv1/SSLv3 cipher=DHE-DSS-AES256-SHA bits=256 verify=NO); Tue, 23 Dec 2014 14:10:33 -0700 (MST) Received: from localhost (500@localhost [local]); by localhost (OpenSMTPD) with ESMTPA id 5803014b; Tue, 23 Dec 2014 20:57:11 +0000 (GMT) Date: Tue, 23 Dec 2014 20:57:11 +0000 From: Miod Vallat To: Theo de Raadt , dlg@openbsd.org Subject: tsciic Message-ID: <20141223205711.GV20210@tazenat.gentiane.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.23 (2014-03-12) Status: RO Content-Length: 13892 Lines: 432 This diff adds i2c bus support to the DS2x/ES4x northbridges. David, can you get this a run on your ES45? My results so far: - ES40: nothing is found because the sensors are either directly connected to the RMC, or the RMC finds a way to claim the bus from the Tsunami. - DS20: one spdmem record per memory bank, but bogus (reports 1/4th of the bank size and a speed of PC66). Probably not reliable; I will tinker with memory setups to confirm this. - DS20L: one spdmem record per memory stick, and two lmenv with some useful information (some voltage sensors report zero but the rest seems legit according to Theo) - DS10, DS25: to be tested eventually - CS20: don't have, no guinea pig to test either - ES45: that's for you to test David, I expect similar disappointing results as on ES40. Index: share/man/man4/iic.4 =================================================================== RCS file: /cvs/src/share/man/man4/iic.4,v retrieving revision 1.82 diff -u -p -r1.82 iic.4 --- share/man/man4/iic.4 16 Jul 2013 16:05:49 -0000 1.82 +++ share/man/man4/iic.4 23 Dec 2014 19:17:19 -0000 @@ -37,6 +37,7 @@ .Cd "iic* at viapm? # amd64 i386" .Cd "iic* at gpioiic? # i386" .Cd "iic* at gdiumiic? # loongson" +.Cd "iic* at tsciic? # alpha" .Sh DESCRIPTION .Tn I2C is a two-wire bus developed by Philips used for connecting Index: share/man/man4/man4.alpha/Makefile =================================================================== RCS file: /cvs/src/share/man/man4/man4.alpha/Makefile,v retrieving revision 1.17 diff -u -p -r1.17 Makefile --- share/man/man4/man4.alpha/Makefile 4 Sep 2011 20:10:16 -0000 1.17 +++ share/man/man4/man4.alpha/Makefile 23 Dec 2014 19:17:22 -0000 @@ -2,7 +2,7 @@ MAN= apecs.4 asc.4 autoconf.4 bba.4 cia.4 intro.4 irongate.4 \ lca.4 le.4 mem.4 mcbus.4 mcpcia.4 scc.4 tcasic.4 \ - tga.4 tsc.4 + tga.4 tsc.4 tsciic.4 MLINKS= mem.4 kmem.4 \ tsc.4 tsp.4 \ mcbus.4 mcmem.4 Index: share/man/man4/man4.alpha/tsc.4 =================================================================== RCS file: /cvs/src/share/man/man4/man4.alpha/tsc.4,v retrieving revision 1.7 diff -u -p -r1.7 tsc.4 --- share/man/man4/man4.alpha/tsc.4 2 Oct 2009 18:01:47 -0000 1.7 +++ share/man/man4/man4.alpha/tsc.4 23 Dec 2014 19:17:22 -0000 @@ -36,13 +36,14 @@ DECchip 21272 and 21274 Core Logic chipset .Sh SYNOPSIS .Cd "tsc* at mainbus?" +.Cd "tsciic* at tsc?" .Cd "tsp* at tsc?" .Cd "pci* at tsp?" .Sh DESCRIPTION The .Nm driver provides support for the DECchip 21272 (Tsunami) and -21274 (Titan) Core Logic chipset found on most 21264-based +21274 (Titan) Core Logic chipsets found on most 21264-based systems. .Pp The @@ -55,7 +56,8 @@ PCI buses, the second one with AGP capab .Sh SEE ALSO .Xr intro 4 , .\".Xr mainbus 4 , -.Xr pci 4 +.Xr pci 4 , +.Xr tsciic 4 .Sh BUGS The AGP capabilities of the second PCI bus of DECchip 21274 are not currently supported. Index: share/man/man4/man4.alpha/tsciic.4 =================================================================== RCS file: share/man/man4/man4.alpha/tsciic.4 diff -N share/man/man4/man4.alpha/tsciic.4 --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ share/man/man4/man4.alpha/tsciic.4 23 Dec 2014 19:17:22 -0000 @@ -0,0 +1,48 @@ +.\" $OpenBSD$ +.\" $NetBSD: tsciic.4,v 1.1 2014/02/21 12:26:00 jdc Exp $ +.\" +.\" Copyright (c) 2013 The NetBSD Foundation, Inc. +.\" All rights reserved. +.\" +.\" This code is derived from software contributed to The NetBSD Foundation +.\" by Julian Coleman +.\" +.\" Redistribution and use in source and binary forms, with or without +.\" modification, are permitted provided that the following conditions +.\" are met: +.\" 1. Redistributions of source code must retain the above copyright +.\" notice, this list of conditions and the following disclaimer. +.\" 2. Redistributions in binary form must reproduce the above copyright +.\" notice, this list of conditions and the following disclaimer in the +.\" documentation and/or other materials provided with the distribution. +.\" +.\" THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS +.\" ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +.\" TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +.\" PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS +.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +.\" POSSIBILITY OF SUCH DAMAGE. +.\" +.Dd $Mdocdate$ +.Dt TSCIIC 4 alpha +.Os +.Sh NAME +.Nm tsciic +.Nd DECchip 21272 and 21274 Core Logic chipset I2C controller +.Sh SYNOPSIS +.Cd "tsciic* at tsc?" +.Cd "iic* at tsciic?" +.Sh DESCRIPTION +The +.Nm +driver provides support for the I2C controller on the DECchip 21272 and 21274 +Core Logic chipsets, on systems without remote management consoles. +.Sh SEE ALSO +.Xr iic 4 , +.Xr intro 4 , +.Xr tsc 4 Index: sys/arch/alpha/conf/GENERIC =================================================================== RCS file: /cvs/src/sys/arch/alpha/conf/GENERIC,v retrieving revision 1.250 diff -u -p -r1.250 GENERIC --- sys/arch/alpha/conf/GENERIC 11 Dec 2014 19:44:16 -0000 1.250 +++ sys/arch/alpha/conf/GENERIC 23 Dec 2014 19:17:31 -0000 @@ -281,6 +281,8 @@ ukphy* at mii? # "unknown" PHYs # sensors alipm* at pci? disable iic* at alipm? +tsciic* at tsc? +iic* at tsciic? adc* at iic? # Analog Devices AD7416/AD7417/7418 admtemp* at iic? # Analog Devices ADM1021 Index: sys/arch/alpha/conf/files.alpha =================================================================== RCS file: /cvs/src/sys/arch/alpha/conf/files.alpha,v retrieving revision 1.100 diff -u -p -r1.100 files.alpha --- sys/arch/alpha/conf/files.alpha 4 Dec 2014 21:03:50 -0000 1.100 +++ sys/arch/alpha/conf/files.alpha 23 Dec 2014 19:17:31 -0000 @@ -212,6 +212,10 @@ device tsc {} attach tsc at mainbus file arch/alpha/pci/tsc.c tsc +device tsciic: i2cbus, i2c_bitbang +attach tsciic at tsc +file arch/alpha/pci/tsciic.c tsciic + device tsp: pcibus, alpha_sgmap, alpha_pci_sgmap_pte64 attach tsp at tsc file arch/alpha/pci/tsp_dma.c tsp Index: sys/arch/alpha/pci/tsc.c =================================================================== RCS file: /cvs/src/sys/arch/alpha/pci/tsc.c,v retrieving revision 1.15 diff -u -p -r1.15 tsc.c --- sys/arch/alpha/pci/tsc.c 2 Oct 2009 18:01:47 -0000 1.15 +++ sys/arch/alpha/pci/tsc.c 23 Dec 2014 19:17:33 -0000 @@ -156,6 +156,10 @@ tscattach(parent, self, aux) config_found(self, &tsp, tscprint); } } + + tsp.tsp_name = "tsciic"; + tsp.tsp_slot = -1; + config_found(self, &tsp, tscprint); } static int @@ -167,7 +171,8 @@ tscprint(aux, p) if (p) printf("%s at %s", tsp->tsp_name, p); - printf(" hose %d", tsp->tsp_slot); + if (tsp->tsp_slot >= 0) + printf(" hose %d", tsp->tsp_slot); return UNCONF; } Index: sys/arch/alpha/pci/tsciic.c =================================================================== RCS file: sys/arch/alpha/pci/tsciic.c diff -N sys/arch/alpha/pci/tsciic.c --- /dev/null 1 Jan 1970 00:00:00 -0000 +++ sys/arch/alpha/pci/tsciic.c 23 Dec 2014 19:17:33 -0000 @@ -0,0 +1,207 @@ +/* $OpenBSD$ */ +/* $NetBSD: tsciic.c,v 1.1 2014/02/21 12:23:30 jdc Exp $ */ + +/* + * Copyright (c) 2013 The NetBSD Foundation, Inc. + * All rights reserved. + * + * This code is derived from software contributed to The NetBSD Foundation + * by Julian Coleman. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS + * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED + * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS + * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include +#include +#include + +#include +#include + +#include +#include + +struct tsciic_softc { + struct device sc_dev; + + bus_space_tag_t sc_iot; + bus_space_handle_t sc_ioh; + + struct i2c_controller sc_i2c_tag; + struct rwlock sc_i2c_lock; +}; + +int tsciic_match(struct device *, void *, void *); +void tsciic_attach(struct device *, struct device *, void *); + +const struct cfattach tsciic_ca = { + .ca_devsize = sizeof(struct tsciic_softc), + .ca_match = tsciic_match, + .ca_attach = tsciic_attach +}; + +struct cfdriver tsciic_cd = { + .cd_name = "tsciic", + .cd_class = DV_DULL +}; + +/* I2C glue */ +int tsciic_acquire_bus(void *, int); +void tsciic_release_bus(void *, int); +int tsciic_send_start(void *, int); +int tsciic_send_stop(void *, int); +int tsciic_initiate_xfer(void *, i2c_addr_t, int); +int tsciic_read_byte(void *, uint8_t *, int); +int tsciic_write_byte(void *, uint8_t, int); + +/* I2C bitbang glue */ +void tsciicbb_set_bits(void *, uint32_t); +void tsciicbb_set_dir(void *, uint32_t); +uint32_t tsciicbb_read(void *); + +#define MPD_BIT_SDA 0x01 +#define MPD_BIT_SCL 0x02 +static const struct i2c_bitbang_ops tsciicbb_ops = { + .ibo_set_bits = tsciicbb_set_bits, + .ibo_set_dir = tsciicbb_set_dir, + .ibo_read_bits = tsciicbb_read, + .ibo_bits = { + [I2C_BIT_SDA] MPD_BIT_SDA, + [I2C_BIT_SCL] MPD_BIT_SCL + } +}; + +int +tsciic_match(struct device *parent, void *match, void *aux) +{ + struct tsp_attach_args *tsp = (struct tsp_attach_args *)aux; + + return strcmp(tsp->tsp_name, tsciic_cd.cd_name) == 0; +} + +void +tsciic_attach(struct device *parent, struct device *self, void *aux) +{ + struct tsciic_softc *sc = (struct tsciic_softc *)self; + struct i2cbus_attach_args iba; + + printf("\n"); + + rw_init(&sc->sc_i2c_lock, "tsciiclk"); + sc->sc_i2c_tag.ic_cookie = sc; + sc->sc_i2c_tag.ic_acquire_bus = tsciic_acquire_bus; + sc->sc_i2c_tag.ic_release_bus = tsciic_release_bus; + sc->sc_i2c_tag.ic_send_start = tsciic_send_start; + sc->sc_i2c_tag.ic_send_stop = tsciic_send_stop; + sc->sc_i2c_tag.ic_initiate_xfer = tsciic_initiate_xfer; + sc->sc_i2c_tag.ic_read_byte = tsciic_read_byte; + sc->sc_i2c_tag.ic_write_byte = tsciic_write_byte; + + memset(&iba, 0, sizeof iba); + iba.iba_name = "iic"; + iba.iba_tag = &sc->sc_i2c_tag; + config_found(self, &iba, iicbus_print); +} + +int +tsciic_acquire_bus(void *cookie, int flags) +{ + struct tsciic_softc *sc = cookie; + + if (cold || (flags & I2C_F_POLL)) + return 0; + + return rw_enter(&sc->sc_i2c_lock, RW_WRITE | RW_INTR); +} + +void +tsciic_release_bus(void *cookie, int flags) +{ + struct tsciic_softc *sc = cookie; + + if (cold || (flags & I2C_F_POLL)) + return; + + rw_exit(&sc->sc_i2c_lock); +} + +int +tsciic_send_start(void *cookie, int flags) +{ + return i2c_bitbang_send_start(cookie, flags, &tsciicbb_ops); +} + +int +tsciic_send_stop(void *cookie, int flags) +{ + return i2c_bitbang_send_stop(cookie, flags, &tsciicbb_ops); +} + +int +tsciic_initiate_xfer(void *cookie, i2c_addr_t addr, int flags) +{ + return i2c_bitbang_initiate_xfer(cookie, addr, flags, &tsciicbb_ops); +} + +int +tsciic_read_byte(void *cookie, uint8_t *valp, int flags) +{ + return i2c_bitbang_read_byte(cookie, valp, flags, &tsciicbb_ops); +} + +int +tsciic_write_byte(void *cookie, uint8_t val, int flags) +{ + return i2c_bitbang_write_byte(cookie, val, flags, &tsciicbb_ops); +} + +/* I2C bitbanging */ +void +tsciicbb_set_bits(void *cookie, uint32_t bits) +{ + uint64_t val; + + val = (bits & MPD_BIT_SDA ? MPD_DS : 0) | + (bits & MPD_BIT_SCL ? MPD_CKS : 0); + alpha_mb(); + STQP(TS_C_MPD) = val; + alpha_mb(); +} + +void +tsciicbb_set_dir(void *cookie, uint32_t dir) +{ + /* Nothing to do */ +} + +uint32_t +tsciicbb_read(void *cookie) +{ + uint64_t val; + uint32_t bits; + + val = LDQP(TS_C_MPD); + bits = (val & MPD_DR ? MPD_BIT_SDA : 0) | + (val & MPD_CKR ? MPD_BIT_SCL : 0); + return bits; +} Index: sys/arch/alpha/pci/tsreg.h =================================================================== RCS file: /cvs/src/sys/arch/alpha/pci/tsreg.h,v retrieving revision 1.5 diff -u -p -r1.5 tsreg.h --- sys/arch/alpha/pci/tsreg.h 2 Oct 2009 18:01:47 -0000 1.5 +++ sys/arch/alpha/pci/tsreg.h 23 Dec 2014 19:17:33 -0000 @@ -94,6 +94,11 @@ #define TS_C_MPD 0x101##a000##00c0UL +# define MPD_DR 0x08 /* RO: Data receive */ +# define MPD_CKR 0x04 /* RO: Clock receive */ +# define MPD_DS 0x02 /* WO: Data send - Must be a 1 to receive */ +# define MPD_CKS 0x01 /* WO: Clock send */ + #define TS_C_AAR0 0x101##a000##0100UL #define TS_C_AAR1 0x101##a000##0140UL #define TS_C_AAR2 0x101##a000##0180UL