Index: alpha/interrupt.c
===================================================================
RCS file: /cvs/src/sys/arch/alpha/alpha/interrupt.c,v
retrieving revision 1.37
diff -u -p -r1.37 interrupt.c
--- alpha/interrupt.c	13 Sep 2015 20:37:28 -0000	1.37
+++ alpha/interrupt.c	7 Jun 2016 03:29:22 -0000
@@ -602,7 +602,7 @@ intr_barrier(void *cookie)
 }
 
 int
-_splraise(int s)
+splraise(int s)
 {
 	int cur = alpha_pal_rdps() & ALPHA_PSL_IPL_MASK;
 	return (s > cur ? alpha_pal_swpipl(s) : cur);
Index: alpha/mutex.c
===================================================================
RCS file: /cvs/src/sys/arch/alpha/alpha/mutex.c,v
retrieving revision 1.15
diff -u -p -r1.15 mutex.c
--- alpha/mutex.c	21 Sep 2015 05:38:58 -0000	1.15
+++ alpha/mutex.c	7 Jun 2016 03:29:22 -0000
@@ -58,7 +58,7 @@ mtx_enter_try(struct mutex *mtx)
 	int s;
 
 	if (mtx->mtx_wantipl != IPL_NONE)
-		s = _splraise(mtx->mtx_wantipl);
+		s = splraise(mtx->mtx_wantipl);
 
 	owner = atomic_cas_ptr(&mtx->mtx_owner, NULL, ci);
 #ifdef DIAGNOSTIC
@@ -91,7 +91,7 @@ mtx_enter(struct mutex *mtx)
 		panic("mtx %p: locking against myself", mtx);
 #endif
 	if (mtx->mtx_wantipl != IPL_NONE)
-		mtx->mtx_oldipl = _splraise(mtx->mtx_wantipl);
+		mtx->mtx_oldipl = splraise(mtx->mtx_wantipl);
 
 	mtx->mtx_owner = ci;
 
Index: include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/alpha/include/intr.h,v
retrieving revision 1.45
diff -u -p -r1.45 intr.h
--- include/intr.h	13 Sep 2015 20:37:28 -0000	1.45
+++ include/intr.h	7 Jun 2016 03:29:22 -0000
@@ -169,23 +169,23 @@ void splassert_check(int, const char *);
     ((s) == ALPHA_PSL_IPL_0 ? spl0() : alpha_pal_swpipl(s))
 
 /* IPL-raising functions/macros */
-int _splraise(int);
+int splraise(int);
 
-#define splsoft()		_splraise(IPL_SOFTINT)
+#define splsoft()		splraise(IPL_SOFTINT)
 #define splsoftserial()		splsoft()
 #define splsoftclock()		splsoft()
 #define splsoftnet()		splsoft()
-#define splnet()		_splraise(IPL_NET)
-#define splbio()		_splraise(IPL_BIO)
-#define spltty()		_splraise(IPL_TTY)
-#define splserial()		_splraise(IPL_SERIAL)
-#define splaudio()		_splraise(IPL_AUDIO)
-#define splvm()			_splraise(IPL_VM)
-#define splclock()		_splraise(IPL_CLOCK)
-#define splstatclock()		_splraise(IPL_CLOCK)
-#define splsched()		_splraise(IPL_SCHED)
-#define splipi()		_splraise(IPL_IPI)
-#define splhigh()		_splraise(IPL_HIGH)
+#define splnet()		splraise(IPL_NET)
+#define splbio()		splraise(IPL_BIO)
+#define spltty()		splraise(IPL_TTY)
+#define splserial()		splraise(IPL_SERIAL)
+#define splaudio()		splraise(IPL_AUDIO)
+#define splvm()			splraise(IPL_VM)
+#define splclock()		splraise(IPL_CLOCK)
+#define splstatclock()		splraise(IPL_CLOCK)
+#define splsched()		splraise(IPL_SCHED)
+#define splipi()		splraise(IPL_IPI)
+#define splhigh()		splraise(IPL_HIGH)
 
 #define spllock()		splhigh()
 
Index: landisk/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/landisk/include/intr.h,v
retrieving revision 1.11
diff -u -p -r1.11 intr.h
--- landisk/include/intr.h	17 May 2013 19:38:52 -0000	1.11
+++ landisk/include/intr.h	7 Jun 2016 23:34:33 -0000
@@ -47,17 +47,18 @@
 
 #define	IPL_MPSAFE	0	/* no "mpsafe" interrupts */
 
-#define	splsoftclock()		_cpu_intr_raise(IPL_SOFTCLOCK << 4)
-#define	splsoftnet()		_cpu_intr_raise(IPL_SOFTNET << 4)
-#define	splsoftserial()		_cpu_intr_raise(IPL_SOFTSERIAL << 4)
-#define	splbio()		_cpu_intr_raise(IPL_BIO << 4)
-#define	splnet()		_cpu_intr_raise(IPL_NET << 4)
-#define	spltty()		_cpu_intr_raise(IPL_TTY << 4)
-#define	splvm()			_cpu_intr_raise(IPL_VM << 4)
-#define	splaudio()		_cpu_intr_raise(IPL_AUDIO << 4)
-#define	splclock()		_cpu_intr_raise(IPL_CLOCK << 4)
+#define splraise(_ipl)		_cpu_intr_raise((_ipl) << 4)
+#define	splsoftclock()		splraise(IPL_SOFTCLOCK)
+#define	splsoftnet()		splraise(IPL_SOFTNET)
+#define	splsoftserial()		splraise(IPL_SOFTSERIAL)
+#define	splbio()		splraise(IPL_BIO)
+#define	splnet()		splraise(IPL_NET)
+#define	spltty()		splraise(IPL_TTY)
+#define	splvm()			splraise(IPL_VM)
+#define	splaudio()		splraise(IPL_AUDIO)
+#define	splclock()		splraise(IPL_CLOCK)
 #define	splstatclock()		splclock()
-#define	splsched()		_cpu_intr_raise(IPL_SCHED << 4)
+#define	splsched()		splraise(IPL_SCHED)
 #define	splhigh()		_cpu_intr_suspend()
 #define	spllock()		splhigh()
 
Index: luna88k/cbus/cbus.c
===================================================================
RCS file: /cvs/src/sys/arch/luna88k/cbus/cbus.c,v
retrieving revision 1.5
diff -u -p -r1.5 cbus.c
--- luna88k/cbus/cbus.c	3 Mar 2015 23:50:36 -0000	1.5
+++ luna88k/cbus/cbus.c	7 Jun 2016 23:34:33 -0000
@@ -252,7 +252,7 @@ cbus_isrdispatch(int intlevel)
 		return;
 	}
 
-	s = raiseipl(ci->isr_ipl);	/* splraise() */
+	s = splraise(ci->isr_ipl);
 	rc = ci->isr_func(ci->isr_arg);
 	splx(s);
 
Index: luna88k/luna88k/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/luna88k/luna88k/machdep.c,v
retrieving revision 1.118
diff -u -p -r1.118 machdep.c
--- luna88k/luna88k/machdep.c	21 Oct 2015 07:59:18 -0000	1.118
+++ luna88k/luna88k/machdep.c	7 Jun 2016 23:34:33 -0000
@@ -1261,7 +1261,7 @@ setipl(int level)
 }
 
 int
-raiseipl(int level)
+splraise(int level)
 {
 	u_int curspl, psr;
 #ifdef MULTIPROCESSOR
Index: m88k/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/m88k/include/intr.h,v
retrieving revision 1.12
diff -u -p -r1.12 intr.h
--- m88k/include/intr.h	21 Dec 2010 14:56:24 -0000	1.12
+++ m88k/include/intr.h	7 Jun 2016 23:34:33 -0000
@@ -67,7 +67,7 @@
 #ifndef _LOCORE
 int	getipl(void);
 int	setipl(int level);
-int	raiseipl(int level);
+int	splraise(int);
 int	spl0(void);
 
 /* SPL asserts */
@@ -92,15 +92,15 @@ void splassert_check(int, const char *);
 
 #endif /* _LOCORE */
 
-#define splsoftclock()		raiseipl(IPL_SOFTINT)
-#define splsoftnet()		raiseipl(IPL_SOFTINT)
-#define splbio()		raiseipl(IPL_BIO)
-#define splnet()		raiseipl(IPL_NET)
-#define spltty()		raiseipl(IPL_TTY)
-#define splclock()		raiseipl(IPL_CLOCK)
-#define splstatclock()		raiseipl(IPL_STATCLOCK)
-#define	splsched()		raiseipl(IPL_SCHED)
-#define splvm()			raiseipl(IPL_VM)
+#define splsoftclock()		splraise(IPL_SOFTINT)
+#define splsoftnet()		splraise(IPL_SOFTINT)
+#define splbio()		splraise(IPL_BIO)
+#define splnet()		splraise(IPL_NET)
+#define spltty()		splraise(IPL_TTY)
+#define splclock()		splraise(IPL_CLOCK)
+#define splstatclock()		splraise(IPL_STATCLOCK)
+#define	splsched()		splraise(IPL_SCHED)
+#define splvm()			splraise(IPL_VM)
 #define splhigh()		setipl(IPL_HIGH)
 
 #define	spllock()		splhigh()
Index: m88k/m88k/mutex.S
===================================================================
RCS file: /cvs/src/sys/arch/m88k/m88k/mutex.S,v
retrieving revision 1.14
diff -u -p -r1.14 mutex.S
--- m88k/m88k/mutex.S	3 Jul 2015 15:12:49 -0000	1.14
+++ m88k/m88k/mutex.S	7 Jun 2016 23:34:33 -0000
@@ -55,7 +55,7 @@ ENTRY(mtx_enter)
 enter_again:
 	ld	%r2,  %r2,  MTX_WANTIPL
 	bcnd	eq0,  %r2,  1f
-	bsr	_C_LABEL(raiseipl)	/* raiseipl(mtx->mtx_wantipl) */
+	bsr	_C_LABEL(splraise)	/* splraise(mtx->mtx_wantipl) */
 1:
 	ld	%r4,  %r31, 0
 	or	%r3,  %r0,  1
@@ -112,7 +112,7 @@ enter_panic:
 	st	%r2,  %r31, 0		/* save mtx */
 	ld	%r2,  %r2,  MTX_WANTIPL
 	bcnd	eq0,  %r2,  1f
-	bsr	_C_LABEL(raiseipl)	/* raiseipl(mtx->mtx_wantipl) */
+	bsr	_C_LABEL(splraise)	/* splraise(mtx->mtx_wantipl) */
 1:
 	ld	%r4,  %r31, 0
 	ldcr	%r3,  CPU
@@ -148,7 +148,7 @@ ENTRY(mtx_enter_try)
 enter_try_again:
 	ld	%r2,  %r2,  MTX_WANTIPL
 	bcnd	eq0,  %r2,  1f
-	bsr	_C_LABEL(raiseipl)	/* raiseipl(mtx->mtx_wantipl) */
+	bsr	_C_LABEL(splraise)	/* splraise(mtx->mtx_wantipl) */
 1:
 	ld	%r4,  %r31, 0
 	or	%r3,  %r0,  1
@@ -205,7 +205,7 @@ enter_try_panic:
 	st	%r2,  %r31, 0		/* save mtx */
 	ld	%r2,  %r2,  MTX_WANTIPL
 	bcnd	eq0,  %r2,  1f
-	bsr	_C_LABEL(raiseipl)	/* raiseipl(mtx->mtx_wantipl) */
+	bsr	_C_LABEL(splraise)	/* splraise(mtx->mtx_wantipl) */
 1:
 	ld	%r4,  %r31, 0
 	ldcr	%r3,  CPU
Index: m88k/m88k/trap.c
===================================================================
RCS file: /cvs/src/sys/arch/m88k/m88k/trap.c,v
retrieving revision 1.103
diff -u -p -r1.103 trap.c
--- m88k/m88k/trap.c	13 Sep 2015 11:32:29 -0000	1.103
+++ m88k/m88k/trap.c	7 Jun 2016 23:34:33 -0000
@@ -1629,7 +1629,7 @@ splassert_check(int wantipl, const char 
 		 * This will raise the spl,
 		 * in a feeble attempt to reduce further damage.
 		 */
-		(void)raiseipl(wantipl);
+		(void)splraise(wantipl);
 	}
 }
 #endif
Index: sparc/include/psl.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc/include/psl.h,v
retrieving revision 1.28
diff -u -p -r1.28 psl.h
--- sparc/include/psl.h	29 Mar 2014 18:09:30 -0000	1.28
+++ sparc/include/psl.h	7 Jun 2016 23:34:33 -0000
@@ -142,28 +142,6 @@ setpsr(newpsr)
 	__asm volatile("nop");
 }
 
-static __inline int
-spl0()
-{
-	int psr, oldipl;
-
-	/*
-	 * wrpsr xors two values: we choose old psr and old ipl here,
-	 * which gives us the same value as the old psr but with all
-	 * the old PIL bits turned off.
-	 */
-	__asm volatile("rd %%psr,%0" : "=r" (psr));
-	oldipl = psr & PSR_PIL;
-	__asm volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
-
-	/*
-	 * Three instructions must execute before we can depend
-	 * on the bits to be changed.
-	 */
-	__asm volatile("nop; nop; nop");
-	return (oldipl);
-}
-
 #ifdef DIAGNOSTIC
 /*
  * Although this function is implemented in MI code, it must be in this MD
@@ -183,83 +161,11 @@ void splassert_check(int, const char *);
 #define splsoftassert(wantipl)	do { /* nada */ } while (0)
 #endif
 
-/*
- * PIL 1 through 14 can use this macro.
- * (spl0 and splhigh are special since they put all 0s or all 1s
- * into the ipl field.)
- */
-#define	SPL(name, newipl) \
-static __inline int name(void); \
-static __inline int name() \
-{ \
-	int psr, oldipl; \
-	__asm volatile("rd %%psr,%0" : "=r" (psr)); \
-	oldipl = psr & PSR_PIL; \
-	psr &= ~oldipl; \
-	__asm volatile("wr %0,%1,%%psr" : : \
-	    "r" (psr), "n" ((newipl) << 8)); \
-	__asm volatile("nop; nop; nop"); \
-	__asm volatile("":::"memory");	/* protect from reordering */ \
-	return (oldipl); \
-}
-/* A non-priority-decreasing version of SPL */
-#define	SPLHOLD(name, newipl) \
-static __inline int name(void); \
-static __inline int name() \
-{ \
-	int psr, oldipl; \
-	__asm volatile("rd %%psr,%0" : "=r" (psr)); \
-	oldipl = psr & PSR_PIL; \
-	if ((newipl << 8) <= oldipl) \
-		return oldipl; \
-	psr &= ~oldipl; \
-	__asm volatile("wr %0,%1,%%psr" : : \
-	    "r" (psr), "n" ((newipl) << 8)); \
-	__asm volatile("nop; nop; nop"); \
-	__asm volatile("":::"memory");	/* protect from reordering */ \
-	return (oldipl); \
-}
-
-SPLHOLD(splsoftint, IPL_SOFTINT)
-#define	splsoftclock		splsoftint
-#define	splsoftnet		splsoftint
-SPLHOLD(splausoft, IPL_AUSOFT)
-SPLHOLD(splfdsoft, IPL_FDSOFT)
-SPLHOLD(splbio, IPL_BIO)
-SPLHOLD(splnet, IPL_NET)
-SPLHOLD(spltty, IPL_TTY)
-SPLHOLD(splvm, IPL_VM)
-SPLHOLD(splclock, IPL_CLOCK)
-SPLHOLD(splfd, IPL_FD)
-SPLHOLD(splzs, IPL_ZS)
-SPLHOLD(splaudio, IPL_AUHARD)
-SPLHOLD(splsched, IPL_SCHED)
-SPLHOLD(splstatclock, IPL_STATCLOCK)
-
-static __inline int splhigh()
-{
-	int psr, oldipl;
-
-	__asm volatile("rd %%psr,%0" : "=r" (psr));
-	__asm volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL));
-	__asm volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) : \
-	    "r" (psr), "n" (PSR_PIL));
-	__asm volatile("":::"memory");	/* protect from reordering */
-	return (oldipl);
-}
-
-/* splx does not have a return value */
-static __inline void splx(newipl)
-	int newipl;
-{
-	int psr;
+int	spl0(void);
+int	splraise(int);
+int	splhigh(int);
+void	splx(int);
 
-	__asm volatile("":::"memory");	/* protect from reordering */
-	__asm volatile("rd %%psr,%0" : "=r" (psr));
-	__asm volatile("wr %0,%1,%%psr" : : \
-	    "r" (psr & ~PSR_PIL), "rn" (newipl));
-	__asm volatile("nop; nop; nop");
-}
 #endif /* KERNEL && !_LOCORE */
 
 #endif /* PSR_IMPL */
Index: sparc/sparc/intr.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc/sparc/intr.c,v
retrieving revision 1.43
diff -u -p -r1.43 intr.c
--- sparc/sparc/intr.c	10 Dec 2015 19:48:04 -0000	1.43
+++ sparc/sparc/intr.c	7 Jun 2016 23:34:33 -0000
@@ -544,3 +544,70 @@ splassert_check(int wantipl, const char 
 	}
 }
 #endif
+
+int
+spl0(void)
+{
+	int psr, oldipl;
+
+	/*
+	 * wrpsr xors two values: we choose old psr and old ipl here,
+	 * which gives us the same value as the old psr but with all
+	 * the old PIL bits turned off.
+	 */
+	__asm volatile("rd %%psr,%0" : "=r" (psr));
+	oldipl = psr & PSR_PIL;
+	__asm volatile("wr %0,%1,%%psr" : : "r" (psr), "r" (oldipl));
+
+	/*
+	 * Three instructions must execute before we can depend
+	 * on the bits to be changed.
+	 */
+	__asm volatile("nop; nop; nop");
+	return (oldipl);
+}
+
+int
+splraise(int newipl)
+{
+	int psr, oldipl;
+
+	newipl <<= 8;
+
+	__asm volatile("rd %%psr,%0" : "=r" (psr));
+	oldipl = psr & PSR_PIL;
+	if (newipl <= oldipl)
+		return oldipl;
+
+	psr &= ~oldipl;
+	__asm volatile("wr %0,%1,%%psr" : : "r" (psr), "n" (newipl));
+	__asm volatile("nop; nop; nop");
+	__asm volatile("":::"memory");	/* protect from reordering */ \
+
+	return (oldipl);
+}
+
+int
+splhigh(void)
+{
+	int psr, oldipl;
+
+	__asm volatile("rd %%psr,%0" : "=r" (psr));
+	__asm volatile("wr %0,0,%%psr" : : "r" (psr | PSR_PIL));
+	__asm volatile("and %1,%2,%0; nop; nop" : "=r" (oldipl) :
+	    "r" (psr), "n" (PSR_PIL));
+	__asm volatile("":::"memory");	/* protect from reordering */
+	return (oldipl);
+}
+
+void
+splx(int newipl)
+{
+	int psr;
+
+	__asm volatile("":::"memory");	/* protect from reordering */
+	__asm volatile("rd %%psr,%0" : "=r" (psr));
+	__asm volatile("wr %0,%1,%%psr" : :
+	    "r" (psr & ~PSR_PIL), "rn" (newipl));
+	__asm volatile("nop; nop; nop");
+}
Index: sparc64/include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/include/intr.h,v
retrieving revision 1.18
diff -u -p -r1.18 intr.h
--- sparc64/include/intr.h	27 Sep 2015 11:29:20 -0000	1.18
+++ sparc64/include/intr.h	7 Jun 2016 23:34:33 -0000
@@ -83,8 +83,29 @@ void    intr_establish(int, struct intrh
 #define	IPL_STATCLOCK	PIL_STATCLOCK	/* statclock */
 #define	IPL_HIGH	PIL_HIGH	/* everything */
 
+#define spl0()		_spl(IPL_NONE)
+#define splsoftint()	_splraise(IPL_SOFTINT)
+#define splsoftclock()	_splraise(IPL_SOFTCLOCK)
+#define splsoftnet()	_splraise(IPL_SOFTNET)
+#define splbio()	_splraise(IPL_BIO)
+#define splnet()	_splraise(IPL_NET)
+#define splsofttty()	_splraise(IPL_SOFTTTY)
+#define spltty()	_splraise(IPL_TTY)
+#define splvm()		_splraise(IPL_VM)
+#define splaudio()	_splraise(IPL_AUDIO)
+#define splclock()	_splraise(IPL_CLOCK)
+#define splserial()	_splraise(IPL_SERIAL)
+#define splsched()	_splraise(IPL_SCHED)
+#define spllock()	_splraise(IPL_LOCK)
+#define splstatclock()	_splraise(IPL_STATCLOCK)
+#define splhigh()	_splraise(IPL_HIGH)
+#define splx(_oldipl)	_splx(_oldipl)
+
+#define splzs()		splserial()
+
 #define	IPL_MPSAFE	0x100
 
+int	 splraise(int);
 void	 intr_barrier(void *);
 
 void	*softintr_establish(int, void (*)(void *), void *);
Index: sparc64/include/psl.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/include/psl.h,v
retrieving revision 1.30
diff -u -p -r1.30 psl.h
--- sparc64/include/psl.h	7 Jun 2016 06:37:33 -0000	1.30
+++ sparc64/include/psl.h	7 Jun 2016 23:34:33 -0000
@@ -1,4 +1,4 @@
-/*	$OpenBSD: psl.h,v 1.30 2016/06/07 06:37:33 dlg Exp $	*/
+/*	$OpenBSD: psl.h,v 1.29 2016/03/07 13:21:51 naddy Exp $	*/
 /*	$NetBSD: psl.h,v 1.20 2001/04/13 23:30:05 thorpej Exp $ */
 
 /*
@@ -317,156 +317,39 @@ stxa_sync(u_int64_t va, u_int64_t asi, u
 	intr_restore(s);
 }
 
-/*
- * GCC pseudo-functions for manipulating PIL
- */
+static inline int
+_spl(int newipl)
+{
+	int oldpil;
 
-#ifdef SPLDEBUG
-void prom_printf(const char *fmt, ...);
-extern int printspl;
-#define SPLPRINT(x)	if(printspl) { int i=10000000; prom_printf x ; while(i--); }
-#define	SPL(name, newpil)						\
-extern __inline int name##X(const char *, int);				\
-extern __inline int name##X(const char *file, int line)			\
-{									\
-	u_int64_t oldpil = sparc_rdpr(pil);				\
-	SPLPRINT(("{%s:%d %d=>%d}", file, line, oldpil, newpil));	\
-	sparc_wrpr(pil, newpil, 0);					\
-	return (oldpil);						\
-}
-/* A non-priority-decreasing version of SPL */
-#define	SPLHOLD(name, newpil) \
-extern __inline int name##X(const char *, int);				\
-extern __inline int name##X(const char * file, int line)		\
-{									\
-	int oldpil = sparc_rdpr(pil);					\
-	if (__predict_false((u_int64_t)newpil <= oldpil))		\
-		return (oldpil);					\
-	SPLPRINT(("{%s:%d %d->!d}", file, line, oldpil, newpil));	\
-	sparc_wrpr(pil, newpil, 0);					\
-	return (oldpil);						\
-}
+	__asm volatile(	"    rdpr %%pil, %0		\n"
+			"    wrpr %%g0, %1, %%pil	\n"
+	    : "=&r" (oldpil)
+	    : "I" (newipl)
+	    : "%g0");
+	__asm volatile("" : : : "memory");
 
-#else
-#define SPLPRINT(x)	
-#define	SPL(name, newpil)						\
-extern __inline int name(void);						\
-extern __inline int name()						\
-{									\
-	int oldpil;							\
-	__asm volatile("    rdpr %%pil, %0		\n"		\
-			 "    wrpr %%g0, %1, %%pil	\n"		\
-	    : "=&r" (oldpil)						\
-	    : "n" (newpil)						\
-	    : "%g0");							\
-	__asm volatile("" : : : "memory");				\
-	return (oldpil);						\
+	return (oldpil);
 }
-/* A non-priority-decreasing version of SPL */
-#define	SPLHOLD(name, newpil)						\
-extern __inline int name(void);						\
-extern __inline int name()						\
-{									\
-	int oldpil;							\
-									\
-	if (newpil <= 1) {						\
-		__asm volatile("    rdpr	%%pil, %0	\n"	\
-				 "    brnz,pn	%0, 1f		\n"	\
-				 "     nop			\n"	\
-				 "    wrpr	%%g0, %1, %%pil	\n"	\
-				 "1:				\n"	\
-	    : "=&r" (oldpil)						\
-	    : "I" (newpil)						\
-	    : "%g0");							\
-	} else {							\
-		__asm volatile("    rdpr	%%pil, %0	\n"	\
-				 "    cmp	%0, %1 - 1	\n"	\
-				 "    bgu,pn	%%xcc, 1f	\n"	\
-				 "     nop			\n"	\
-				 "    wrpr	%%g0, %1, %%pil	\n"	\
-				 "1:				\n"	\
-	    : "=&r" (oldpil)						\
-	    : "I" (newpil)						\
-	    : "cc");							\
-	}								\
-	__asm volatile("" : : : "memory");				\
-	return (oldpil);						\
-}
-#endif
-
-SPL(spl0, 0)
-
-SPLHOLD(splsoftint, 1)
-#define	splsoftclock	splsoftint
-#define	splsoftnet	splsoftint
-
-/* Block devices */
-SPLHOLD(splbio, PIL_BIO)
-
-/* network hardware interrupts are at level 6 */
-SPLHOLD(splnet, PIL_NET)
 
-/* tty input runs at software level 6 */
-SPLHOLD(spltty, PIL_TTY)
-
-/*
- * Memory allocation (must be as high as highest network, tty, or disk device)
- */
-SPLHOLD(splvm, PIL_VM)
-
-SPLHOLD(splclock, PIL_CLOCK)
-
-/* fd hardware interrupts are at level 11 */
-SPLHOLD(splfd, PIL_FD)
+/* A non-priority-decreasing version of SPL */
+static inline int
+_splraise(int newpil)
+{
+	int oldpil;
 
-/* zs hardware interrupts are at level 12 */
-SPLHOLD(splzs, PIL_SER)
-SPLHOLD(splserial, PIL_SER)
-
-/* audio hardware interrupts are at level 13 */
-SPLHOLD(splaudio, PIL_AUD)
-
-/* second sparc timer interrupts at level 14 */
-SPLHOLD(splstatclock, PIL_STATCLOCK)
-
-SPLHOLD(splsched, PIL_SCHED)
-SPLHOLD(spllock, PIL_LOCK)
-
-SPLHOLD(splhigh, PIL_HIGH)
-
-/* splx does not have a return value */
-#ifdef SPLDEBUG
-
-#define	spl0()		spl0X(__FILE__, __LINE__)
-#define	splsoftint()	splsoftintX(__FILE__, __LINE__)
-#define	splbio()	splbioX(__FILE__, __LINE__)
-#define	splnet()	splnetX(__FILE__, __LINE__)
-#define	spltty()	splttyX(__FILE__, __LINE__)
-#define	splvm()		splvmX(__FILE__, __LINE__)
-#define	splclock()	splclockX(__FILE__, __LINE__)
-#define	splfd()		splfdX(__FILE__, __LINE__)
-#define	splzs()		splzsX(__FILE__, __LINE__)
-#define	splserial()	splzerialX(__FILE__, __LINE__)
-#define	splaudio()	splaudioX(__FILE__, __LINE__)
-#define	splstatclock()	splstatclockX(__FILE__, __LINE__)
-#define	splsched()	splschedX(__FILE__, __LINE__)
-#define	spllock()	spllockX(__FILE__, __LINE__)
-#define	splhigh()	splhighX(__FILE__, __LINE__)
-#define splx(x)		splxX((x),__FILE__, __LINE__)
+	oldpil = sparc_rdpr(pil);
+	if (newpil > oldpil)
+		sparc_wrpr(pil, newpil, 0);
+        return (oldpil);
+}
 
-extern __inline void splxX(u_int64_t, const char *, int);
-extern __inline void
-splxX(u_int64_t newpil, const char *file, int line)
-#else
-extern __inline void splx(int newpil)
-#endif
+static inline void
+_splx(int newpil)
 {
-#ifdef SPLDEBUG
-	u_int64_t oldpil = sparc_rdpr(pil);
-	SPLPRINT(("{%d->%d}", oldpil, newpil));
-#endif
 	sparc_wrpr(pil, newpil, 0);
 }
+
 #endif /* KERNEL && !_LOCORE */
 
 #endif /* _SPARC64_PSL_ */
Index: sparc64/sparc64/intr.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/sparc64/intr.c,v
retrieving revision 1.54
diff -u -p -r1.54 intr.c
--- sparc64/sparc64/intr.c	27 Sep 2015 11:29:20 -0000	1.54
+++ sparc64/sparc64/intr.c	7 Jun 2016 23:34:33 -0000
@@ -313,6 +313,12 @@ intr_establish(int level, struct intrhan
 	splx(s);
 }
 
+int
+splraise(int ipl)
+{
+	return (_splraise(ipl));
+}
+
 void
 intr_barrier(void *cookie)
 {