Index: arch/sparc64/dev/iommu.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/dev/iommu.c,v
retrieving revision 1.74
diff -u -p -r1.74 iommu.c
--- arch/sparc64/dev/iommu.c	30 Apr 2017 16:45:45 -0000	1.74
+++ arch/sparc64/dev/iommu.c	12 May 2017 01:25:37 -0000
@@ -296,7 +296,7 @@ strbuf_reset(struct strbuf_ctl *sb)
 	bus_space_write_8(sb->sb_bustag, sb->sb_sb,
 	    STRBUFREG(strbuf_ctl), STRBUF_EN);
 
-	membar(Lookaside);
+	__membar("#Lookaside");
 
 	/* No streaming buffers? Disable them */
 	if (bus_space_read_8(sb->sb_bustag, sb->sb_sb,
@@ -412,7 +412,7 @@ iommu_remove(struct iommu_state *is, str
 	 * IO operations are strongly ordered WRT each other.  It is
 	 * unclear how they relate to normal memory accesses.
 	 */
-	membar(StoreStore);
+	__membar("#StoreStore");
 
 	IOMMUREG_WRITE(is, iommu_flush, va);
 
@@ -529,7 +529,7 @@ iommu_strbuf_flush_done(struct iommu_map
 	 * memory is initialized before the IOMMU uses it.
 	 * Is this Needed?  How are IO and memory operations ordered? 
 	 */
-	membar(StoreStore);
+	__membar("#StoreStore");
 
 	bus_space_write_8(sb->sb_bustag, sb->sb_sb,
 		    STRBUFREG(strbuf_flushsync), sf->sbf_flushpa);
@@ -538,7 +538,7 @@ iommu_strbuf_flush_done(struct iommu_map
 	    ("iommu_strbuf_flush_done: flush = %llx pa = %lx\n", 
 		ldxa(sf->sbf_flushpa, ASI_PHYS_CACHED), sf->sbf_flushpa));
 
-	membar(StoreLoad | Lookaside);
+	__membar("#StoreLoad | #Lookaside");
 
 	for(;;) {
 		int i;
@@ -549,7 +549,7 @@ iommu_strbuf_flush_done(struct iommu_map
 		 * fetches.
 		 */
 		for (i = 0; i < 1000; ++i) {
-			membar(LoadLoad);
+			__membar("#LoadLoad");
 			/* Bypass non-coherent D$ */
 			/* non-coherent...?   Huh? */
 			flush = ldxa(sf->sbf_flushpa, ASI_PHYS_CACHED);
@@ -1560,14 +1560,14 @@ iommu_dvmamap_sync(bus_dma_tag_t t, bus_
 		return;
 
 	if (ops & BUS_DMASYNC_PREWRITE)
-		membar(MemIssue);
+		__membar("#MemIssue");
 
 	if ((ims->ims_flags & IOMMU_MAP_STREAM) &&
 	    (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_PREWRITE)))
 		_iommu_dvmamap_sync(t, t0, map, offset, len, ops);
 
 	if (ops & BUS_DMASYNC_POSTREAD)
-		membar(MemIssue);
+		__membar("#MemIssue");
 }
 
 /*
Index: arch/sparc64/dev/psycho.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/dev/psycho.c,v
retrieving revision 1.74
diff -u -p -r1.74 psycho.c
--- arch/sparc64/dev/psycho.c	23 Aug 2016 03:28:01 -0000	1.74
+++ arch/sparc64/dev/psycho.c	12 May 2017 01:25:37 -0000
@@ -1120,11 +1120,11 @@ psycho_conf_read(pci_chipset_tag_t pc, p
 	int s;
 
 	s = splhigh();
-	membar(Sync);
+	__membar("#Sync");
 	ci->ci_pci_probe = 1;
 	val = bus_space_read_4(pc->bustag, pc->bushandle,
 	    PCITAG_OFFSET(tag) + reg);
-	membar(Sync);
+	__membar("#Sync");
 	if (ci->ci_pci_fault)
 		val = 0xffffffff;
 	ci->ci_pci_probe = ci->ci_pci_fault = 0;
@@ -1333,7 +1333,7 @@ psycho_sabre_dvmamap_sync(bus_dma_tag_t 
 		psycho_psychoreg_read(sc, pci_dma_write_sync);
 
 	if (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_PREWRITE))
-		membar(MemIssue);
+		__membar("#MemIssue");
 }
 
 u_int
Index: arch/sparc64/dev/pyro.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/dev/pyro.c,v
retrieving revision 1.30
diff -u -p -r1.30 pyro.c
--- arch/sparc64/dev/pyro.c	20 Dec 2016 13:40:50 -0000	1.30
+++ arch/sparc64/dev/pyro.c	12 May 2017 01:25:37 -0000
@@ -372,11 +372,11 @@ pyro_conf_read(pci_chipset_tag_t pc, pci
 	int s;
 
 	s = splhigh();
-	membar(Sync);
+	__membar("#Sync");
 	ci->ci_pci_probe = 1;
 	val = bus_space_read_4(pc->bustag, pc->bushandle,
 	    (PCITAG_OFFSET(tag) << 4) + reg);
-	membar(Sync);
+	__membar("#Sync");
 	if (ci->ci_pci_fault)
 		val = 0xffffffff;
 	ci->ci_pci_probe = ci->ci_pci_fault = 0;
Index: arch/sparc64/dev/schizo.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/dev/schizo.c,v
retrieving revision 1.67
diff -u -p -r1.67 schizo.c
--- arch/sparc64/dev/schizo.c	23 Aug 2016 03:28:01 -0000	1.67
+++ arch/sparc64/dev/schizo.c	12 May 2017 01:25:37 -0000
@@ -476,11 +476,11 @@ schizo_conf_read(pci_chipset_tag_t pc, p
 	int s;
 
 	s = splhigh();
-	membar(Sync);
+	__membar("#Sync");
 	ci->ci_pci_probe = 1;
 	val = bus_space_read_4(pc->bustag, pc->bushandle,
 	    PCITAG_OFFSET(tag) + reg);
-	membar(Sync);
+	__membar("#Sync");
 	if (ci->ci_pci_fault)
 		val = 0xffffffff;
 	ci->ci_pci_probe = ci->ci_pci_fault = 0;
Index: arch/sparc64/dev/vdsk.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/dev/vdsk.c,v
retrieving revision 1.47
diff -u -p -r1.47 vdsk.c
--- arch/sparc64/dev/vdsk.c	13 Oct 2016 18:16:42 -0000	1.47
+++ arch/sparc64/dev/vdsk.c	12 May 2017 01:25:37 -0000
@@ -1093,7 +1093,7 @@ vdsk_submit_cmd(struct scsi_xfer *xs)
 	sc->sc_vd->vd_desc[desc].offset = lba;
 	sc->sc_vd->vd_desc[desc].size = xs->datalen;
 	sc->sc_vd->vd_desc[desc].ncookies = ncookies;
-	membar(Sync);
+	membar_sync();
 	sc->sc_vd->vd_desc[desc].hdr.dstate = VIO_DESC_READY;
 
 	sc->sc_vsd[desc].vsd_xs = xs;
Index: arch/sparc64/dev/viommu.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/dev/viommu.c,v
retrieving revision 1.18
diff -u -p -r1.18 viommu.c
--- arch/sparc64/dev/viommu.c	30 Apr 2017 16:45:45 -0000	1.18
+++ arch/sparc64/dev/viommu.c	12 May 2017 01:25:37 -0000
@@ -884,7 +884,7 @@ viommu_dvmamap_sync(bus_dma_tag_t t, bus
 		return;
 
 	if (ops & BUS_DMASYNC_PREWRITE)
-		membar(MemIssue);
+		__membar("#MemIssue");
 
 #if 0
 	if (ops & (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_PREWRITE))
@@ -892,7 +892,7 @@ viommu_dvmamap_sync(bus_dma_tag_t t, bus
 #endif
 
 	if (ops & BUS_DMASYNC_POSTREAD)
-		membar(MemIssue);
+		__membar("#MemIssue");
 }
 
 int
Index: arch/sparc64/include/atomic.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/include/atomic.h,v
retrieving revision 1.13
diff -u -p -r1.13 atomic.h
--- arch/sparc64/include/atomic.h	18 Jul 2014 12:44:53 -0000	1.13
+++ arch/sparc64/include/atomic.h	12 May 2017 01:25:37 -0000
@@ -142,11 +142,13 @@ atomic_clearbits_int(volatile unsigned i
 	} while (r != e);
 }
 
-#define membar_enter()		membar(StoreLoad|StoreStore)
-#define membar_exit()		membar(LoadStore|StoreStore)
-#define membar_producer()	membar(StoreStore)
-#define membar_consumer()	membar(LoadLoad)
-#define membar_sync()		membar(Sync)
+#define __membar(_m)		__asm volatile("membar " _m ::: "memory")
+
+#define membar_enter()		__membar("#StoreLoad|#StoreStore")
+#define membar_exit()		__membar("#LoadStore|#StoreStore")
+#define membar_producer()	__membar("#StoreStore")
+#define membar_consumer()	__membar("#LoadLoad")
+#define membar_sync()		__membar("#Sync")
 
 #endif /* defined(_KERNEL) */
 #endif /* _MACHINE_ATOMIC_H_ */
Index: arch/sparc64/include/bus.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/include/bus.h,v
retrieving revision 1.31
diff -u -p -r1.31 bus.h
--- arch/sparc64/include/bus.h	13 Feb 2017 01:34:37 -0000	1.31
+++ arch/sparc64/include/bus.h	12 May 2017 01:25:37 -0000
@@ -66,7 +66,7 @@
 #ifndef _MACHINE_BUS_H_
 #define _MACHINE_BUS_H_
 
-#include <machine/ctlreg.h>
+#include <sys/atomic.h>
 
 /*
  * Debug hooks
@@ -319,19 +319,19 @@ bus_space_barrier(t, h, o, s, f)
 #ifdef notyet
 	switch (f) {
 	case (BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE):
-		membar(LoadLoad|StoreStore);
+		__membar("#LoadLoad|#StoreStore");
 		break;
 	case BUS_SPACE_BARRIER_READ:
-		membar(LoadLoad);
+		membar("#LoadLoad");
 		break;
 	case BUS_SPACE_BARRIER_WRITE:
-		membar(StoreStore);
+		membar("#StoreStore");
 		break;
 	default:
 		break;
 	}
 #else
-	membar(Sync);
+	__membar("#Sync");
 #endif
 }
 
Index: arch/sparc64/include/ctlreg.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/include/ctlreg.h,v
retrieving revision 1.27
diff -u -p -r1.27 ctlreg.h
--- arch/sparc64/include/ctlreg.h	7 Mar 2016 13:21:51 -0000	1.27
+++ arch/sparc64/include/ctlreg.h	12 May 2017 01:25:37 -0000
@@ -58,24 +58,6 @@
  */
 
 /*
- * membar operand macros for use in other macros when # is a special
- * character.  Keep these in sync with what the hardware expects.
- */
-#define C_Lookaside     (0)
-#define C_MemIssue      (1)
-#define C_Sync          (2)
-#define M_LoadLoad      (0)
-#define M_StoreLoad     (1)
-#define M_LoadStore     (2)
-#define M_StoreStore    (3)
-
-#define CMASK_SHIFT     (4)
-#define MMASK_SHIFT     (0)
-
-#define CMASK_GEN(bit)  ((1 << (bit)) << CMASK_SHIFT)
-#define MMASK_GEN(bit)  ((1 << (bit)) << MMASK_SHIFT)
-
-/*
  * The Alternate address spaces. 
  * 
  * 0x00-0x7f are privileged 
@@ -521,22 +503,6 @@
  * Apparently the definition of bypass ASIs is that they all use the 
  * D$ so we need to flush the D$ to make sure we don't get data pollution.
  */
-
-#define sparc_membar(mask) do {						\
-	if (mask)							\
-		__asm volatile("membar %0" : : "n" (mask) : "memory");	\
-	else								\
-		__asm volatile("" : : : "memory");			\
-} while(0)
-
-#define membar sparc_membar
-#define Lookaside       CMASK_GEN(C_Lookaside)
-#define MemIssue        CMASK_GEN(C_MemIssue)
-#define Sync            CMASK_GEN(C_Sync)
-#define LoadLoad        MMASK_GEN(M_LoadLoad)
-#define StoreLoad       MMASK_GEN(M_StoreLoad)
-#define LoadStore       MMASK_GEN(M_LoadStore)
-#define StoreStore      MMASK_GEN(M_StoreStore)
 
 #define sparc_wr(name, val, xor)					\
 do {									\
Index: arch/sparc64/include/psl.h
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/include/psl.h,v
retrieving revision 1.31
diff -u -p -r1.31 psl.h
--- arch/sparc64/include/psl.h	13 Jun 2016 01:08:13 -0000	1.31
+++ arch/sparc64/include/psl.h	12 May 2017 01:25:37 -0000
@@ -313,7 +313,7 @@ stxa_sync(u_int64_t va, u_int64_t asi, u
 {
 	u_int64_t s = intr_disable();
 	stxa_nc(va, asi, val);
-	membar(Sync);
+	__asm volatile("membar #Sync" : : : "memory");
 	intr_restore(s);
 }
 
Index: arch/sparc64/sparc64/cpu.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/sparc64/cpu.c,v
retrieving revision 1.65
diff -u -p -r1.65 cpu.c
--- arch/sparc64/sparc64/cpu.c	3 May 2016 08:30:15 -0000	1.65
+++ arch/sparc64/sparc64/cpu.c	12 May 2017 01:25:37 -0000
@@ -717,7 +717,7 @@ cpu_boot_secondary_processors(void)
 		}
 
 		for (i = 0; i < 2000; i++) {
-			sparc_membar(Sync);
+			membar_sync();
 			if (ci->ci_flags & CPUF_RUNNING)
 				break;
 			delay(10000);
@@ -734,7 +734,7 @@ cpu_hatch(void)
 	cpu_init(ci);
 
 	ci->ci_flags |= CPUF_RUNNING;
-	sparc_membar(Sync);
+	membar_sync();
 
 	s = splhigh();
 	nanouptime(&ci->ci_schedstate.spc_runtime);
Index: arch/sparc64/sparc64/ipifuncs.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/sparc64/ipifuncs.c,v
retrieving revision 1.15
diff -u -p -r1.15 ipifuncs.c
--- arch/sparc64/sparc64/ipifuncs.c	10 May 2014 12:29:58 -0000	1.15
+++ arch/sparc64/sparc64/ipifuncs.c	12 May 2017 01:25:37 -0000
@@ -97,7 +97,7 @@ sun4u_send_ipi(int itid, void (*func)(vo
 		stxa(IDDR_1H, ASI_INTERRUPT_DISPATCH, arg0);
 		stxa(IDDR_2H, ASI_INTERRUPT_DISPATCH, arg1);
 		stxa(IDCR(itid), ASI_INTERRUPT_DISPATCH, 0);
-		membar(Sync);
+		membar_sync();
 
 		for (j = 0; j < 1000000; j++) {
 			if (ldxa(0, ASR_IDSR) & (IDSR_BUSY << shift))
Index: arch/sparc64/sparc64/lock_machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/sparc64/lock_machdep.c,v
retrieving revision 1.14
diff -u -p -r1.14 lock_machdep.c
--- arch/sparc64/sparc64/lock_machdep.c	30 Apr 2017 16:45:45 -0000	1.14
+++ arch/sparc64/sparc64/lock_machdep.c	12 May 2017 01:25:37 -0000
@@ -58,7 +58,7 @@ extern int __mp_lock_spinout;
  * On SPARC64 VI and its successors we execute the processor-specific
  * sleep instruction.
  */
-static __inline void
+void
 __mp_lock_spin_hook(void)
 {
 	__asm volatile(
@@ -84,8 +84,6 @@ __mp_lock_spin_hook(void)
 		: : : "memory");
 }
 
-#define SPINLOCK_SPIN_HOOK __mp_lock_spin_hook()
-
 static __inline void
 __mp_lock_spin(struct __mp_lock *mpl, u_int me)
 {
@@ -119,7 +117,7 @@ __mp_lock(struct __mp_lock *mpl)
 	intr_restore(s);
 
 	__mp_lock_spin(mpl, cpu->mplc_ticket);
-	sparc_membar(LoadLoad | LoadStore);
+	membar_enter();
 }
 
 void
@@ -130,7 +128,7 @@ __mp_unlock(struct __mp_lock *mpl)
 
 	s = intr_disable();
 	if (--cpu->mplc_depth == 0) {
-		sparc_membar(StoreStore | LoadStore);
+		membar_exit();
 		mpl->mpl_ticket++;
 	}
 	intr_restore(s);
@@ -146,7 +144,7 @@ __mp_release_all(struct __mp_lock *mpl)
 	s = intr_disable();
 	rv = cpu->mplc_depth;
 	cpu->mplc_depth = 0;
-	sparc_membar(StoreStore | LoadStore);
+	membar_exit();
 	mpl->mpl_ticket++;
 	intr_restore(s);
 
Index: arch/sparc64/sparc64/machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/sparc64/machdep.c,v
retrieving revision 1.183
diff -u -p -r1.183 machdep.c
--- arch/sparc64/sparc64/machdep.c	21 Jan 2017 05:42:03 -0000	1.183
+++ arch/sparc64/sparc64/machdep.c	12 May 2017 01:25:37 -0000
@@ -1327,7 +1327,7 @@ _bus_dmamap_sync(t, t0, map, offset, len
 	int ops;
 {
 	if (ops & (BUS_DMASYNC_PREWRITE | BUS_DMASYNC_POSTREAD))
-		membar(MemIssue);
+		__membar("#MemIssue");
 }
 
 /*
Index: arch/sparc64/sparc64/vm_machdep.c
===================================================================
RCS file: /cvs/src/sys/arch/sparc64/sparc64/vm_machdep.c,v
retrieving revision 1.37
diff -u -p -r1.37 vm_machdep.c
--- arch/sparc64/sparc64/vm_machdep.c	30 Apr 2017 16:45:45 -0000	1.37
+++ arch/sparc64/sparc64/vm_machdep.c	12 May 2017 01:25:37 -0000
@@ -314,7 +314,7 @@ fpusave_proc(struct proc *p, int save)
 		sparc64_send_ipi(ci->ci_itid,
 		    save ? ipi_save_fpstate : ipi_drop_fpstate, (vaddr_t)p, 0);
 		while(ci->ci_fpproc == p)
-			sparc_membar(Sync);
+			membar_sync();
 		break;
 	}
 #else
Index: dev/pci/drm/drmP.h
===================================================================
RCS file: /cvs/src/sys/dev/pci/drm/drmP.h,v
retrieving revision 1.209
diff -u -p -r1.209 drmP.h
--- dev/pci/drm/drmP.h	8 Oct 2016 05:52:06 -0000	1.209
+++ dev/pci/drm/drmP.h	12 May 2017 01:25:37 -0000
@@ -158,7 +158,7 @@ extern struct cfdriver drm_cd;
 #elif defined(__sparc64__)
 #define DRM_READMEMORYBARRIER()		DRM_MEMORYBARRIER() 
 #define DRM_WRITEMEMORYBARRIER()	DRM_MEMORYBARRIER()
-#define DRM_MEMORYBARRIER()		membar(Sync)
+#define DRM_MEMORYBARRIER()		membar_sync()
 #endif
 
 #define smp_mb__before_atomic_dec()	DRM_MEMORYBARRIER()