/* $OpenBSD$ */ /* * Copyright (c) 2023 David Gwynne * * Permission to use, copy, modify, and distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include /* * RK3568 eMMC */ #define EMMC_VER_ID 0x500 #define EMMC_VER_TYPE 0x504 #define EMMC_HOST_CTRL3 0x508 /* B */ #define EMMC_HOST_CTRL3_CMD_CONFLICT_CHECK (1U << 0) #define EMMC_HOST_CTRL3_SW_CG_DIS (1U << 4) #define EMMC_EMMC_CTRL 0x52c /* HW */ #define EMMC_EMMC_CTRL_CARD_IS_EMMC (1U << 0) #define EMMC_EMMC_CTRL_DISABLE_DATA_CRC_CHK (1U << 1) #define EMMC_EMMC_CTRL_EMMC_RST_N (1U << 2) #define EMMC_EMMC_CTRL_EMMC_RST_N_OE (1U << 3) #define EMMC_EMMC_CTRL_ENH_STROBE_ENABLE (1U << 8) #define EMMC_EMMC_CTRL_CQE_ALGO_SEL (1U << 9) #define EMMC_EMMC_CTRL_CQE_PREFETCH_DISABLE (1U << 10) #define EMMC_BOOT_CTRL 0x52e /* HW */ #define EMMC_BOOT_CTRL_MAN_BOOT_EN (1U << 0) #define EMMC_BOOT_CTRL_VALIDATE_BOOT (1U << 1) #define EMMC_BOOT_CTRL_BOOT_ACK_ENABLE (1U << 8) #define EMMC_BOOT_CTRL_BOOT_TOUT_CNT_SHIFT 12 #define EMMC_BOOT_CTRL_BOOT_TOUT_CNT_MASK 0xf #define EMMC_AT_CTRL 0x540 #define EMMC_AT_CTRL_SWIN_TH_EN (1U << 2) #define EMMC_AT_CTRL_RPT_TUNE_ERR (1U << 3) #define EMMC_AT_CTRL_SW_TUNE_EN (1U << 4) #define EMMC_AT_CTRL_TUNE_CLK_STOP_EN (1U << 16) #define EMMC_AT_CTRL_PRE_CHANGE_DLY_MASK (0x3 << 17) #define EMMC_AT_CTRL_PRE_CHANGE_DLY_LT1 (0x0 << 17) #define EMMC_AT_CTRL_PRE_CHANGE_DLY_LT2 (0x1 << 17) #define EMMC_AT_CTRL_PRE_CHANGE_DLY_LT3 (0x2 << 17) #define EMMC_AT_CTRL_PRE_CHANGE_DLY_LT4 (0x3 << 17) #define EMMC_AT_CTRL_POST_CHANGE_DLY_MASK (0x3 << 19) #define EMMC_AT_CTRL_POST_CHANGE_DLY_LT1 (0x0 << 19) #define EMMC_AT_CTRL_POST_CHANGE_DLY_LT2 (0x1 << 19) #define EMMC_AT_CTRL_POST_CHANGE_DLY_LT3 (0x2 << 19) #define EMMC_AT_CTRL_POST_CHANGE_DLY_LT4 (0x3 << 19) #define EMMC_AT_STAT 0x544 #define EMMC_AT_STAT_CENTER_PH_CODE_SHIFT 0 #define EMMC_AT_STAT_CENTER_PH_CODE_MASK 0xff #define EMMC_AT_STAT_R_EDGE_PH_CODE_SHIFT 8 #define EMMC_AT_STAT_R_EDGE_PH_CODE_MASK 0xff #define EMMC_AT_STAT_L_EDGE_PH_CODE_SHIFT 16 #define EMMC_AT_STAT_L_EDGE_PH_CODE_MASK 0xff #define EMMC_DLL_CTRL 0x800 #define EMMC_DLL_CTRL_DLL_START (1U << 0) #define EMMC_DLL_CTRL_DLL_SRST (1U << 1) #define EMMC_DLL_CTRL_DLL_INCREMENT_SHIFT 8 #define EMMC_DLL_CTRL_DLL_INCREMENT_MASK 0xff #define EMMC_DLL_CTRL_DLL_START_POINT_SHIFT 16 #define EMMC_DLL_CTRL_DLL_START_POINT_MASK 0xff #define EMMC_DLL_CTRL_DLL_BYPASS_MODE (1U << 24) #define EMMC_DLL_RXCLK 0x804 #define EMMC_DLL_RXCLK_RX_TAP_NUM_SHIFT 0 #define EMMC_DLL_RXCLK_RX_TAP_NUM_MASK 0x1f #define EMMC_DLL_RXCLK_RX_TAP_VALUE_SHIFT 8 #define EMMC_DLL_RXCLK_RX_TAP_VALUE_MASK 0xff #define EMMC_DLL_RXCLK_RX_DELAY_NUM_SHIFT 16 #define EMMC_DLL_RXCLK_RX_DELAY_NUM_MASK 0xff #define EMMC_DLL_RXCLK_RX_TAP_NUM_SEL (1U << 24) #define EMMC_DLL_RXCLK_RX_TAP_VALUE_SEL (1U << 25) #define EMMC_DLL_RXCLK_RX_DELAY_NUM_SEL (1U << 26) #define EMMC_DLL_RXCLK_RX_CLK_OUT_SEL (1U << 27) #define EMMC_DLL_RXCLK_RX_CLK_CHANGE_WINDOW (1U << 28) #define EMMC_DLL_RXCLK_RX_CLK_SRC_SEL (1U << 29) #define EMMC_DLL_TXCLK 0x804 #define EMMC_DLL_TXCLK_TX_TAP_NUM_SHIFT 0 #define EMMC_DLL_TXCLK_TX_TAP_NUM_MASK 0x1f #define EMMC_DLL_TXCLK_TX_TAP_VALUE_SHIFT 8 #define EMMC_DLL_TXCLK_TX_TAP_VALUE_MASK 0xff #define EMMC_DLL_TXCLK_TX_DELAY_SHIFT 16 #define EMMC_DLL_TXCLK_TX_DELAY_MASK 0xff #define EMMC_DLL_TXCLK_TX_TAP_NUM_SEL (1U << 24) #define EMMC_DLL_TXCLK_TX_TAP_VALUE_SEL (1U << 25) #define EMMC_DLL_TXCLK_TX_DELAY_SEL (1U << 26) #define EMMC_DLL_TXCLK_TX_CLK_OUT_SEL (1U << 27) #define EMMC_DLL_STRBIN 0x80c #define EMMC_DLL_STRBIN_TAP_NUM_SHIFT 0 #define EMMC_DLL_STRBIN_TAP_NUM_MASK 0x1f #define EMMC_DLL_STRBIN_TAP_VALUE_SHIFT 8 #define EMMC_DLL_STRBIN_TAP_VALUE_MASK 0xff #define EMMC_DLL_STRBIN_DELAY_NUM_SHIFT 16 #define EMMC_DLL_STRBIN_DELAY_NUM_MASK 0xff #define EMMC_DLL_STRBIN_TAP_NUM_SEL (1U << 24) #define EMMC_DLL_STRBIN_TAP_VALUE_SEL (1U << 25) #define EMMC_DLL_STRBIN_DELAY_NUM_SEL (1U << 26) #define EMMC_DLL_STRBIN_DELAY_ENA (1U << 27) #define EMMC_DLL_STATUS0 0x840 #define EMMC_DLL_STATUS0_DLL_LOCK_VALUE_SHIFT 0 #define EMMC_DLL_STATUS0_DLL_LOCK_VALUE_MASK 0xff #define EMMC_DLL_STATUS0_DLL_LOCK (1U << 8) #define EMMC_DLL_STATUS0_DLL_LOCK_TIMEOUT (1U << 9) #define EMMC_DLL_STATUS1 0x844 #define EMMC_DLL_STATUS1_DLL_TXCLK_DELAY_VALUE_SHIFT \ 0 #define EMMC_DLL_STATUS1_DLL_TXCLK_DELAY_VALUE_MASK \ 0xff #define EMMC_DLL_STATUS1_DLL_RXCLK_DELAY_VALUE_SHIFT \ 8 #define EMMC_DLL_STATUS1_DLL_RXCLK_DELAY_VALUE_MASK \ 0xff #define EMMC_DLL_STATUS1_DLL_STRBIN_DELAY_VALUE_SHIFT \ 16 #define EMMC_DLL_STATUS1_DLL_STRBIN_DELAY_VALUE_MASK \ 0xff struct rkemmc_softc { struct device sc_dev; struct device *sc_sdhc; int sc_node; bus_space_tag_t sc_iot; bus_space_handle_t sc_ioh; bus_size_t sc_ios; bus_dma_tag_t sc_dmat; void *sc_ih; struct sdhc_host *sc_host; }; static int rkemmc_match(struct device *, void *, void *); static void rkemmc_attach(struct device *, struct device *, void *); static inline void rkemmc_wr1(struct rkemmc_softc *, bus_size_t, uint8_t); #if 0 static inline void rkemmc_wr2(struct rkemmc_softc *, bus_size_t, uint16_t); #endif static inline uint16_t rkemmc_rd2(struct rkemmc_softc *, bus_size_t); static inline void rkemmc_wr4(struct rkemmc_softc *, bus_size_t, uint32_t); static void rkemmc_clock_pre(struct sdhc_softc *, int, int); static void rkemmc_clock_post(struct sdhc_softc *, int, int); static int rkemmc_non_removable(struct sdhc_softc *); static int rkemmc_signal_voltage(struct sdhc_softc *, int); const struct cfattach rkemmc_ca = { sizeof(struct rkemmc_softc), rkemmc_match, rkemmc_attach }; struct cfdriver rkemmc_cd = { NULL, "rkemmc", DV_DULL }; int rkemmc_match(struct device *parent, void *match, void *aux) { #if 1 struct fdt_attach_args *faa = aux; return (OF_is_compatible(faa->fa_node, "rockchip,rk3568-dwcmshc")); #else return (0); #endif } void rkemmc_attach(struct device *parent, struct device *self, void *aux) { struct rkemmc_softc *sc = (struct rkemmc_softc *)self; struct fdt_attach_args *faa = aux; if (faa->fa_nreg < 1) { printf(": no registers\n"); return; } sc->sc_node = faa->fa_node; sc->sc_iot = faa->fa_iot; sc->sc_ios = faa->fa_reg[0].size; sc->sc_dmat = faa->fa_dmat; if (bus_space_map(sc->sc_iot, faa->fa_reg[0].addr, faa->fa_reg[0].size, 0, &sc->sc_ioh)) { printf(": can't map registers\n"); return; } #if 0 printf(": ver id %08x type %08x\n", bus_space_read_4(sc->sc_iot, sc->sc_ioh, EMMC_VER_ID), bus_space_read_4(sc->sc_iot, sc->sc_ioh, EMMC_VER_TYPE)); #else printf("\n"); #endif pinctrl_byname(sc->sc_node, "default"); clock_set_assigned(sc->sc_node); clock_enable_all(sc->sc_node); reset_deassert_all(sc->sc_node); clock_set_frequency(sc->sc_node, 0, SDMMC_SDCLK_400KHZ * 1000); /* Disable Command Conflict Check */ rkemmc_wr1(sc, EMMC_HOST_CTRL3, 0); /* Disable DLL for identification */ rkemmc_wr4(sc, EMMC_DLL_CTRL, EMMC_DLL_CTRL_DLL_START | EMMC_DLL_CTRL_DLL_BYPASS_MODE); rkemmc_wr4(sc, EMMC_DLL_RXCLK, EMMC_DLL_RXCLK_RX_CLK_SRC_SEL); rkemmc_wr4(sc, EMMC_DLL_TXCLK, 0); rkemmc_wr4(sc, EMMC_DLL_STRBIN, 0); sc->sc_sdhc = config_found(self, aux, NULL); } static int sdhc_rkemmc_match(struct device *, void *, void *); static void sdhc_rkemmc_attach(struct device *, struct device *, void *); const struct cfattach sdhc_rkemmc_ca = { sizeof(struct sdhc_softc), sdhc_rkemmc_match, sdhc_rkemmc_attach }; static int sdhc_rkemmc_match(struct device *parent, void *match, void *aux) { return (1); } static void sdhc_rkemmc_attach(struct device *parent, struct device *self, void *aux) { struct sdhc_softc *sdhc = (struct sdhc_softc *)self; struct rkemmc_softc *sc = (struct rkemmc_softc *)parent; struct fdt_attach_args *faa = aux; uint64_t capmask = ((uint64_t)SDHC_DDR50_SUPP << 32); uint16_t capset = 0; int bus_width; uint32_t freq; sc->sc_ih = fdt_intr_establish(faa->fa_node, IPL_BIO, sdhc_intr, sdhc, DEVNAME(sdhc)); if (sc->sc_ih == NULL) { printf(": can't establish interrupt\n"); return; } printf("\n"); sdhc->sc_host = &sc->sc_host; sdhc->sc_dmat = faa->fa_dmat; sdhc->sc_bus_clock_pre = rkemmc_clock_pre; sdhc->sc_bus_clock_post = rkemmc_clock_post; sdhc->sc_signal_voltage = rkemmc_signal_voltage; if (OF_getpropbool(sc->sc_node, "non-removable")) sdhc->sc_card_detect = rkemmc_non_removable; bus_width = OF_getpropint(faa->fa_node, "bus-width", 1); if (bus_width < 8) SET(capmask, SDHC_8BIT_MODE_SUPP); freq = clock_get_frequency(faa->fa_node, "block"); sdhc->sc_clkbase = freq / 1000; sdhc_host_found(sdhc, sc->sc_iot, sc->sc_ioh, sc->sc_ios, 1, capmask, capset); printf("%s: clock ctrl %04x\n", DEVNAME(sc), rkemmc_rd2(sc, SDHC_CLOCK_CTL)); } static inline struct rkemmc_softc * sdhc_rkemmc(struct sdhc_softc *sdhc) { return ((struct rkemmc_softc *)sdhc->sc_dev.dv_parent); } static void rkemmc_clock_pre(struct sdhc_softc *sdhc, int freq, int timing) { struct rkemmc_softc *sc = sdhc_rkemmc(sdhc); //clock_set_frequency(sc->sc_node, 0, freq * 1000); printf("%s: %s freq %d timing %d -> %u\n", DEVNAME(sc), __func__, freq, timing, clock_get_frequency(sc->sc_node, 0)); } static void rkemmc_clock_post(struct sdhc_softc *sdhc, int freq, int timing) { struct rkemmc_softc *sc = sdhc_rkemmc(sdhc); clock_set_frequency(sc->sc_node, 0, freq * 1000); printf("%s: %s freq %d timing %d -> %u\n", DEVNAME(sc), __func__, freq, timing, clock_get_frequency(sc->sc_node, 0)); } static int rkemmc_non_removable(struct sdhc_softc *sdhc) { return (1); } static int rkemmc_signal_voltage(struct sdhc_softc *sdhc, int signal_voltage) { struct rkemmc_softc *sc = sdhc_rkemmc(sdhc); printf("%s: signal voltage %d\n", DEVNAME(sc), signal_voltage); return (0); } static inline void rkemmc_wr1(struct rkemmc_softc *sc, bus_size_t off, uint8_t v) { bus_space_write_1(sc->sc_iot, sc->sc_ioh, off, v); } #if 0 static inline void rkemmc_wr2(struct rkemmc_softc *sc, bus_size_t off, uint16_t v) { bus_space_write_2(sc->sc_iot, sc->sc_ioh, off, v); } #endif static inline uint16_t rkemmc_rd2(struct rkemmc_softc *sc, bus_size_t off) { return (bus_space_read_2(sc->sc_iot, sc->sc_ioh, off)); } static inline void rkemmc_wr4(struct rkemmc_softc *sc, bus_size_t off, uint32_t v) { bus_space_write_4(sc->sc_iot, sc->sc_ioh, off, v); }