Index: atomic.h =================================================================== RCS file: /cvs/src/sys/arch/powerpc/include/atomic.h,v retrieving revision 1.8 diff -u -p -r1.8 atomic.h --- atomic.h 22 Apr 2015 06:39:03 -0000 1.8 +++ atomic.h 1 May 2015 02:42:59 -0000 @@ -54,15 +54,15 @@ _atomic_cas_uint(volatile unsigned int * unsigned int rv; __asm volatile ( - "1: lwarx %0, 0, %1 \n" - " cmpw 0, %0, %3 \n" + "1: lwarx %0, 0, %2 \n" + " cmpw 0, %0, %4 \n" " bne- 2f \n" - " stwcx. %2, 0, %1 \n" + " stwcx. %3, 0, %2 \n" " bne- 1b \n" "2: \n" - : "=&r" (rv) + : "=&r" (rv), "+m" (*p) : "r" (p), "r" (n), "r" (o) - : "cc", "memory"); + : "cc"); return (rv); } @@ -74,15 +74,15 @@ _atomic_cas_ulong(volatile unsigned long unsigned long rv; __asm volatile ( - "1: lwarx %0, 0, %1 \n" - " cmpw 0, %0, %3 \n" + "1: lwarx %0, 0, %2 \n" + " cmpw 0, %0, %4 \n" " bne- 2f \n" - " stwcx. %2, 0, %1 \n" + " stwcx. %3, 0, %2 \n" " bne- 1b \n" "2: \n" - : "=&r" (rv) + : "=&r" (rv), "+m" (*p) : "r" (p), "r" (n), "r" (o) - : "cc", "memory"); + : "cc"); return (rv); } @@ -95,15 +95,15 @@ _atomic_cas_ptr(volatile void *pp, void void *rv; __asm volatile ( - "1: lwarx %0, 0, %3 \n" - " cmpw 0, %0, %1 \n" + "1: lwarx %0, 0, %2 \n" + " cmpw 0, %0, %4 \n" " bne- 2f \n" - " stwcx. %2, 0, %3 \n" + " stwcx. %3, 0, %2 \n" " bne- 1b \n" "2: \n" - : "=&r" (rv) - : "r" (o), "r" (n), "r" (p) - : "cc", "memory"); + : "=&r" (rv), "+m" (*p) + : "r" (p), "r" (n), "r" (o) + : "cc"); return (rv); } @@ -115,12 +115,12 @@ _atomic_swap_uint(volatile unsigned int unsigned int rv; __asm volatile ( - "1: lwarx %0, 0, %1 \n" - " stwcx. %2, 0, %1 \n" + "1: lwarx %0, 0, %2 \n" + " stwcx. %3, 0, %2 \n" " bne- 1b \n" - : "=&r" (rv) + : "=&r" (rv), "+m" (*p) : "r" (p), "r" (v) - : "cc", "memory"); + : "cc"); return (rv); } @@ -132,12 +132,12 @@ _atomic_swap_ulong(volatile unsigned lon unsigned long rv; __asm volatile ( - "1: lwarx %0, 0, %1 \n" - " stwcx. %2, 0, %1 \n" + "1: lwarx %0, 0, %2 \n" + " stwcx. %3, 0, %2 \n" " bne- 1b \n" - : "=&r" (rv) + : "=&r" (rv), "+m" (*p) : "r" (p), "r" (v) - : "cc", "memory"); + : "cc"); return (rv); } @@ -150,16 +150,16 @@ _atomic_swap_ptr(volatile void *pp, void void *rv; __asm volatile ( - "1: lwarx %0, 0, %1 \n" - " stwcx. %2, 0, %1 \n" + "1: lwarx %0, 0, %2 \n" + " stwcx. %3, 0, %2 \n" " bne- 1b \n" - : "=&r" (rv) + : "=&r" (rv), "+m" (*p) : "r" (p), "r" (v) - : "cc", "memory"); + : "cc"); return (rv); } -#define atomic_swap_ptr(_p, _n) _atomic_swap_ptr((_p), (_n)) +#define atomic_swap_ptr(_p, _v) _atomic_swap_ptr((_p), (_v)) static inline unsigned int _atomic_add_int_nv(volatile unsigned int *p, unsigned int v) @@ -167,18 +167,17 @@ _atomic_add_int_nv(volatile unsigned int unsigned int rv; __asm volatile ( - "1: lwarx %0, 0, %1 \n" - " add %0, %2, %0 \n" - " stwcx. %0, 0, %1 \n" + "1: lwarx %0, 0, %2 \n" + " add %0, %3, %0 \n" + " stwcx. %0, 0, %2 \n" " bne- 1b \n" - : "=&r" (rv) + : "=&r" (rv), "+m" (*p) : "r" (p), "r" (v) - : "cc", "memory"); + : "cc", "xer"); - return (rv + v); + return (rv); } #define atomic_add_int_nv(_p, _v) _atomic_add_int_nv((_p), (_v)) -#define atomic_sub_int_nv(_p, _v) _atomic_add_int_nv((_p), 0 - (_v)) static inline unsigned long _atomic_add_long_nv(volatile unsigned long *p, unsigned long v) @@ -186,18 +185,91 @@ _atomic_add_long_nv(volatile unsigned lo unsigned long rv; __asm volatile ( - "1: lwarx %0, 0, %1 \n" - " add %0, %2, %0 \n" - " stwcx. %0, 0, %1 \n" + "1: lwarx %0, 0, %2 \n" + " add %0, %3, %0 \n" + " stwcx. %0, 0, %2 \n" " bne- 1b \n" - : "=&r" (rv) + : "=&r" (rv), "+m" (*p) : "r" (p), "r" (v) - : "cc", "memory"); + : "cc", "xer"); - return (rv + v); + return (rv); } #define atomic_add_long_nv(_p, _v) _atomic_add_long_nv((_p), (_v)) -#define atomic_sub_long_nv(_p, _v) _atomic_add_long_nv((_p), 0 - (_v)) + +static inline unsigned int +_atomic_sub_int_nv(volatile unsigned int *p, unsigned int v) +{ + unsigned int rv; + + __asm volatile ( + "1: lwarx %0, 0, %2 \n" + " subf %0, %3, %0 \n" + " stwcx. %0, 0, %2 \n" + " bne- 1b \n" + : "=&r" (rv), "+m" (*p) + : "r" (p), "r" (v) + : "cc", "xer"); + + return (rv); +} +#define atomic_sub_int_nv(_p, _v) _atomic_sub_int_nv((_p), (_v)) + +static inline unsigned long +_atomic_sub_long_nv(volatile unsigned long *p, unsigned long v) +{ + unsigned long rv; + + __asm volatile ( + "1: lwarx %0, 0, %2 \n" + " subf %0, %3, %0 \n" + " stwcx. %0, 0, %2 \n" + " bne- 1b \n" + : "=&r" (rv), "+m" (*p) + : "r" (p), "r" (v) + : "cc", "xer"); + + return (rv); +} +#define atomic_sub_long_nv(_p, _v) _atomic_sub_long_nv((_p), (_v)) + +static inline unsigned int +_atomic_addic_int_nv(volatile unsigned int *p, unsigned int v) +{ + unsigned int rv; + + __asm volatile ( + "1: lwarx %0, 0, %2 \n" + " addic %0, %0, %3 \n" + " stwcx. %0, 0, %2 \n" + " bne- 1b \n" + : "=&r" (rv), "+m" (*p) + : "r" (p), "n" (v) + : "cc", "xer"); + + return (rv); +} +#define atomic_inc_int_nv(_p) _atomic_addic_int_nv((_p), 1) +#define atomic_dec_int_nv(_p) _atomic_addic_int_nv((_p), -1) + +static inline unsigned long +_atomic_addic_long_nv(volatile unsigned long *p, unsigned long v) +{ + unsigned long rv; + + __asm volatile ( + "1: lwarx %0, 0, %2 \n" + " addic %0, %0, %3 \n" + " stwcx. %0, 0, %2 \n" + " bne- 1b \n" + : "=&r" (rv), "+m" (*p) + : "r" (p), "n" (v) + : "cc", "xer"); + + return (rv); +} +#define atomic_inc_long_nv(_p) _atomic_addic_long_nv((_p), 1) +#define atomic_dec_long_nv(_p) _atomic_addic_long_nv((_p), -1) #define __membar(_f) do { __asm __volatile(_f ::: "memory"); } while (0)