Index: mvclock.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/mvclock.c,v
retrieving revision 1.12
diff -u -p -r1.12 mvclock.c
--- mvclock.c	17 May 2022 10:09:40 -0000	1.12
+++ mvclock.c	4 Jun 2022 11:59:56 -0000
@@ -252,15 +252,39 @@ cp110_enable(void *cookie, uint32_t *cel
 
 /* Armada 3700 Periph block */
 
-#define PERIPH_NB_MMC			0x0
-#define PERIPH_NB_SQF			0x7
-#define PERIPH_NB_I2C2			0x9
-#define PERIPH_NB_I2C1			0xa
+/* North Bridge clocks */
+#define PERIPH_NB_MMC			0x00
+#define PERIPH_NB_SATA			0x01 /* SATA Host */
+#define PERIPH_NB_SEC_AT		0x02 /* Security AT */
+#define PERIPH_NB_SEC_DAP		0x03 /* Security DAP */
+#define PERIPH_NB_TSECM			0x04 /* Security Engine */
+#define PERIPH_NB_SETM_TMX		0x05 /* Serial Embedded Trace Module */
+#define PERIPH_NB_AVS			0x06 /* Adaptive Voltage Scaling */
+#define PERIPH_NB_SQF			0x07 /* SPI */
+#define PERIPH_NB_I2C2			0x09
+#define PERIPH_NB_I2C1			0x0a
+#define PERIPH_NB_DDR_PHY		0x0b
+#define PERIPH_NB_DDR_FCLK		0x0c
+#define PERIPH_NB_TRACE			0x0d
+#define PERIPH_NB_COUNTER		0x0e
+#define PERIPH_NB_EIO97			0x0f
 #define PERIPH_NB_CPU			0x10
-#define PERIPH_SB_GBE1_CORE		0x7
-#define PERIPH_SB_GBE0_CORE		0x8
-#define PERIPH_SB_USB32_USB2_SYS	0xb
-#define PERIPH_SB_USB32_SS_SYS		0xc
+
+/* South Bridge clocks */
+#define PERIPH_SB_GBE_50		0x00 /* 50MHz parent for gbe */
+#define PERIPH_SB_GBE_CORE		0x01 /* parent for gbe core */
+#define PERIPH_SB_GBE_125		0x02 /* 125MHz parent for gbe */
+#define PERIPH_SB_GBE1_50		0x03 /* 50MHz parent for gbe port 1 */
+#define PERIPH_SB_GBE0_50		0x04 /* 50MHz parent for gbe port 0 */
+#define PERIPH_SB_GBE1_125		0x05 /* 125MHz parent for gbe port 1 */
+#define PERIPH_SB_GBE0_125		0x06 /* 125MHz parent for gbe port 0 */
+#define PERIPH_SB_GBE1_CORE		0x07 /* gbe core port 1 */
+#define PERIPH_SB_GBE0_CORE		0x08 /* gbe core port 0 */
+#define PERIPH_SB_GBE_BM		0x09 /* gbe buffer manager */
+#define PERIPH_SB_SDIO			0x0a
+#define PERIPH_SB_USB32_USB2_SYS	0x0b /* USB 2 clock */
+#define PERIPH_SB_USB32_SS_SYS		0x0c /* USB 3 clock */
+#define PERIPH_SB_PCIE			0x0d
 
 #define PERIPH_TBG_SEL			0x0
 #define  PERIPH_TBG_SEL_MASK			0x3
@@ -354,7 +378,29 @@ a3700_periph_sb_enable(void *cookie, uin
 uint32_t
 a3700_periph_sb_get_frequency(void *cookie, uint32_t *cells)
 {
+	struct mvclock_softc *sc = cookie;
 	uint32_t idx = cells[0];
+	uint32_t freq;
+
+	switch (idx) {
+	case PERIPH_SB_GBE_CORE:
+		freq = a3700_periph_tbg_get_frequency(sc, 8);
+		freq /= a3700_periph_get_double_div(sc,
+		    PERIPH_DIV_SEL1, 18, 21);
+		return freq;
+	case PERIPH_SB_GBE1_CORE:
+		idx = PERIPH_SB_GBE_CORE;
+		freq = a3700_periph_sb_get_frequency(sc, &idx);
+		freq /= a3700_periph_get_div(sc, PERIPH_DIV_SEL1, 13) + 1;
+		return freq;
+	case PERIPH_SB_GBE0_CORE:
+		idx = PERIPH_SB_GBE_CORE;
+		freq = a3700_periph_sb_get_frequency(sc, &idx);
+		freq /= a3700_periph_get_div(sc, PERIPH_DIV_SEL1, 14) + 1;
+		return freq;
+	default:
+		break;
+	}
 
 	printf("%s: 0x%08x\n", __func__, idx);
 	return 0;