Index: include/specialreg.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/specialreg.h,v
retrieving revision 1.109
diff -u -p -r1.109 specialreg.h
--- include/specialreg.h	3 Sep 2023 09:30:43 -0000	1.109
+++ include/specialreg.h	22 Dec 2023 03:00:20 -0000
@@ -245,6 +245,7 @@
 #define SEFF0EDX_SRBDS_CTRL	0x00000200 /* MCU_OPT_CTRL MSR */
 #define SEFF0EDX_MD_CLEAR	0x00000400 /* Microarch Data Clear */
 #define SEFF0EDX_TSXFA		0x00002000 /* TSX Forced Abort */
+#define SEFF0EDX_HYBRID		0x00008000 /* Hybrid part */
 #define SEFF0EDX_IBT		0x00100000 /* Indirect Branch Tracking */
 #define SEFF0EDX_IBRS		0x04000000 /* IBRS / IBPB Speculation Control */
 #define SEFF0EDX_STIBP		0x08000000 /* STIBP Speculation Control */
Index: amd64/identcpu.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/identcpu.c,v
retrieving revision 1.138
diff -u -p -r1.138 identcpu.c
--- amd64/identcpu.c	3 Sep 2023 09:30:43 -0000	1.138
+++ amd64/identcpu.c	22 Dec 2023 03:00:20 -0000
@@ -222,6 +230,7 @@ const struct {
 	{ SEFF0EDX_L1DF,	"L1DF" },
 	 /* SEFF0EDX_ARCH_CAP (not printed) */
 	{ SEFF0EDX_SSBD,	"SSBD" },
+	{ SEFF0EDX_HYBRID,	"HYBRID" },
 }, cpu_tpm_eaxfeatures[] = {
 	{ TPM_SENSOR,		"SENSOR" },
 	{ TPM_ARAT,		"ARAT" },
@@ -883,6 +896,7 @@ cpu_topology(struct cpu_info *ci)
 	u_int32_t apicid, max_apicid = 0, max_coreid = 0;
 	u_int32_t smt_bits = 0, core_bits, pkg_bits = 0;
 	u_int32_t smt_mask = 0, core_mask, pkg_mask = 0;
+	int intel_hybrid = 0;
 
 	/* We need at least apicid at CPUID 1 */
 	if (cpuid_level < 1)
@@ -942,20 +956,51 @@ cpu_topology(struct cpu_info *ci)
 		ci->ci_smt_id = apicid & smt_mask;
 		ci->ci_core_id = (apicid & core_mask) >> smt_bits;
 		ci->ci_pkg_id = (apicid & pkg_mask) >> pkg_bits;
+
+		if (ISSET(ci->ci_feature_sefflags_edx, SEFF0EDX_HYBRID) &&
+		    cpuid_level >= 0x1a)
+			intel_hybrid = 1;
 	} else
 		goto no_topology;
-#ifdef DEBUG
-	printf("cpu%d: smt %u, core %u, pkg %u "
-		"(apicid 0x%x, max_apicid 0x%x, max_coreid 0x%x, smt_bits 0x%x, smt_mask 0x%x, "
-		"core_bits 0x%x, core_mask 0x%x, pkg_bits 0x%x, pkg_mask 0x%x)\n",
-		ci->ci_cpuid, ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id,
-		apicid, max_apicid, max_coreid, smt_bits, smt_mask, core_bits,
-		core_mask, pkg_bits, pkg_mask);
-#else
-	printf("cpu%d: smt %u, core %u, package %u\n", ci->ci_cpuid,
+
+	printf("cpu%d: smt %u, core %u, package %u", ci->ci_cpuid,
 		ci->ci_smt_id, ci->ci_core_id, ci->ci_pkg_id);
 
+	if (intel_hybrid) {
+		char typestr[32];
+		const char *coretypenm = typestr;
+		unsigned int coretype;
+
+		CPUID_LEAF(0x1a, 0, eax, ebx, ecx, edx);
+		if (eax != 0) {
+			coretype = (eax >> 24) & 0xff;
+
+			switch (coretype) {
+			case 0x20:
+				coretypenm = "efficient";
+				break;
+			case 0x40:
+				coretypenm = "performance";
+				break;
+			default:
+				snprintf(typestr, sizeof(typestr),
+				    "unknown type %02xh", coretype);
+				break;
+			}
+
+			printf(", %s core", coretypenm);
+		}
+	}
+
+#ifdef DEBUG
+	printf(" (apicid 0x%x, max_apicid 0x%x, max_coreid 0x%x,"
+	    " smt_bits 0x%x, smt_mask 0x%x, core_bits 0x%x, core_mask 0x%x,"
+	    " pkg_bits 0x%x, pkg_mask 0x%x)",
+	    apicid, max_apicid, max_coreid,
+	    smt_bits, smt_mask, core_bits, core_mask,
+	    pkg_bits, pkg_mask);
 #endif
+	printf("\n");
 	return;
 	/* We can't map, so consider ci_core_id as ci_cpuid */
 no_topology: