Index: amd64/intr.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/intr.c,v
retrieving revision 1.55
diff -u -p -r1.55 intr.c
--- amd64/intr.c	28 Dec 2020 14:23:30 -0000	1.55
+++ amd64/intr.c	5 Nov 2022 17:03:35 -0000
@@ -552,7 +552,10 @@ struct intrhand fake_softclock_intrhand;
 struct intrhand fake_softnet_intrhand;
 struct intrhand fake_softtty_intrhand;
 struct intrhand fake_timer_intrhand;
+#ifdef MULTIPROCESSOR
 struct intrhand fake_ipi_intrhand;
+struct intrhand fake_xcall_intrhand;
+#endif
 #if NXEN > 0
 struct intrhand fake_xen_intrhand;
 #endif
@@ -619,6 +622,17 @@ cpu_intr_init(struct cpu_info *ci)
 	isp->is_handlers = &fake_ipi_intrhand;
 	isp->is_pic = &local_pic;
 	ci->ci_isources[LIR_IPI] = isp;
+
+	isp = malloc(sizeof (struct intrsource), M_DEVBUF, M_NOWAIT|M_ZERO);
+	if (isp == NULL)
+		panic("can't allocate fixed interrupt source");
+	isp->is_recurse = Xxcallintr;
+	isp->is_resume = Xxcallintr;
+	fake_xcall_intrhand.ih_level = IPL_SOFTCLOCK;
+	fake_xcall_intrhand.ih_flags = IPL_MPSAFE;
+	isp->is_handlers = &fake_xcall_intrhand;
+	isp->is_pic = &local_pic;
+	ci->ci_isources[SIR_XCALL] = isp;
 #endif
 #if NXEN > 0
 	isp = malloc(sizeof (struct intrsource), M_DEVBUF, M_NOWAIT|M_ZERO);
Index: amd64/ipifuncs.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/ipifuncs.c,v
retrieving revision 1.36
diff -u -p -r1.36 ipifuncs.c
--- amd64/ipifuncs.c	31 Aug 2021 17:40:59 -0000	1.36
+++ amd64/ipifuncs.c	5 Nov 2022 17:03:35 -0000
@@ -61,6 +61,7 @@
 void x86_64_ipi_nop(struct cpu_info *);
 void x86_64_ipi_halt(struct cpu_info *);
 void x86_64_ipi_wbinvd(struct cpu_info *);
+void x86_64_ipi_xcall(struct cpu_info *);
 
 #if NVMM > 0
 void x86_64_ipi_vmclear_vmm(struct cpu_info *);
@@ -108,6 +109,7 @@ void (*ipifunc[X86_NIPI])(struct cpu_inf
 	NULL,
 #endif
 	x86_64_ipi_wbinvd,
+	x86_64_ipi_xcall,
 };
 
 void
@@ -166,3 +168,13 @@ x86_64_ipi_wbinvd(struct cpu_info *ci)
 {
 	wbinvd();
 }
+
+void
+x86_64_ipi_xcall(struct cpu_info *ci)
+{
+	/*
+	 * this is an inlining of softintr() because we already have
+	 * curcpu() and the SIR_XCALL bit to set.
+	 */
+	x86_atomic_setbits_u64(&ci->ci_ipending, 1UL << SIR_XCALL);
+};
Index: amd64/softintr.c
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/softintr.c,v
retrieving revision 1.10
diff -u -p -r1.10 softintr.c
--- amd64/softintr.c	11 Sep 2020 09:27:09 -0000	1.10
+++ amd64/softintr.c	5 Nov 2022 17:03:35 -0000
@@ -38,6 +38,9 @@
 #include <sys/systm.h>
 #include <sys/malloc.h>
 
+#include <sys/atomic.h>
+#include <sys/task.h>
+
 #include <machine/intr.h>
 
 #include <uvm/uvm_extern.h>
@@ -169,3 +172,58 @@ softintr_disestablish(void *arg)
 
 	free(sih, M_DEVBUF, sizeof(*sih));
 }
+
+void
+#ifdef MULTIPROCESSOR
+cpu_xcall_self(struct task *t)
+#else
+cpu_xcall(struct cpu_info *ci, struct task *t)
+#endif
+{
+	int s = splsoftclock();
+	(*t->t_func)(t->t_arg);
+	splx(s);
+}
+
+#ifdef MULTIPROCESSOR
+void
+cpu_xcall(struct cpu_info *ci, struct task *t)
+{
+	size_t i;
+
+	if (ci == curcpu()) {
+		/* execute the task immediately on the local cpu */
+		cpu_xcall_self(t);
+		return;
+	}
+
+	for (;;) {
+		for (i = 0; i < nitems(ci->ci_xcalls); i++) {
+			if (atomic_cas_ptr(&ci->ci_xcalls[i], NULL, t) != NULL)
+				continue;
+
+			/* membar_producer(); */
+			x86_send_ipi(ci, X86_IPI_XCALL);
+			return;
+		}
+
+		CPU_BUSY_CYCLE();
+	}
+}
+
+void
+cpu_xcall_dispatch(void)
+{
+	struct cpu_info *ci = curcpu();
+	struct task *t;
+	size_t i;
+
+	for (i = 0; i < nitems(ci->ci_xcalls); i++) {
+		t = ci->ci_xcalls[i];
+		if (t != NULL) {
+			ci->ci_xcalls[i] = NULL;
+			(*t->t_func)(t->t_arg);
+		}
+	}
+}
+#endif /* MULTIPROCESSOR */
Index: amd64/vector.S
===================================================================
RCS file: /cvs/src/sys/arch/amd64/amd64/vector.S,v
retrieving revision 1.86
diff -u -p -r1.86 vector.S
--- amd64/vector.S	4 Sep 2021 22:15:33 -0000	1.86
+++ amd64/vector.S	5 Nov 2022 17:03:35 -0000
@@ -1445,3 +1445,12 @@ KIDTVEC(softclock)
 	decl	CPUVAR(IDEPTH)
 	jmp	retpoline_r13
 END(Xsoftclock)
+
+KIDTVEC(xcallintr)
+	movl	$IPL_SOFTCLOCK, CPUVAR(ILEVEL)
+	sti
+	incl	CPUVAR(IDEPTH)
+	call	_C_LABEL(cpu_xcall_dispatch)
+	decl	CPUVAR(IDEPTH)
+	jmp	retpoline_r13
+END(Xsoftclock)
Index: include/cpu.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/cpu.h,v
retrieving revision 1.143
diff -u -p -r1.143 cpu.h
--- include/cpu.h	26 Jun 2022 07:14:55 -0000	1.143
+++ include/cpu.h	5 Nov 2022 17:03:35 -0000
@@ -90,6 +90,11 @@ union vmm_cpu_cap {
 	struct svm vcc_svm;
 };
 
+/*
+ * for xcalls
+ */
+struct task;
+
 struct x86_64_tss;
 struct cpu_info {
 	/*
@@ -192,6 +197,7 @@ struct cpu_info {
 
 #ifdef MULTIPROCESSOR
 	struct srp_hazard	ci_srp_hazards[SRP_HAZARD_NUM];
+	struct task		*ci_xcalls[4];
 #endif
 
 	struct ksensordev	ci_sensordev;
Index: include/intr.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/intr.h,v
retrieving revision 1.33
diff -u -p -r1.33 intr.h
--- include/intr.h	14 Dec 2021 18:16:14 -0000	1.33
+++ include/intr.h	5 Nov 2022 17:03:35 -0000
@@ -207,6 +207,9 @@ void cpu_intr_init(struct cpu_info *);
 void intr_printconfig(void);
 void intr_barrier(void *);
 
+struct task;
+void cpu_xcall(struct cpu_info *ci, struct task *);
+
 #ifdef MULTIPROCESSOR
 void x86_send_ipi(struct cpu_info *, int);
 int x86_fast_ipi(struct cpu_info *, int);
@@ -215,6 +218,8 @@ void x86_ipi_handler(void);
 void x86_setperf_ipi(struct cpu_info *);
 
 extern void (*ipifunc[X86_NIPI])(struct cpu_info *);
+
+extern void Xxcallintr(void);
 #endif
 
 #endif /* !_LOCORE */
Index: include/intrdefs.h
===================================================================
RCS file: /cvs/src/sys/arch/amd64/include/intrdefs.h,v
retrieving revision 1.22
diff -u -p -r1.22 intrdefs.h
--- include/intrdefs.h	31 Aug 2021 17:40:59 -0000	1.22
+++ include/intrdefs.h	5 Nov 2022 17:03:35 -0000
@@ -54,9 +54,10 @@
 #define	SIR_CLOCK	61
 #define	SIR_NET		60
 #define	SIR_TTY		59
+#define	SIR_XCALL	58
 
-#define	LIR_XEN		58
-#define	LIR_HYPERV	57
+#define	LIR_XEN		57
+#define	LIR_HYPERV	56
 
 /*
  * Maximum # of interrupt sources per CPU. 64 to fit in one word.
@@ -84,8 +85,9 @@
 #define X86_IPI_START_VMM		0x00000100
 #define X86_IPI_STOP_VMM		0x00000200
 #define X86_IPI_WBINVD			0x00000400
+#define X86_IPI_XCALL			0x00000800
 
-#define X86_NIPI			12
+#define X86_NIPI			13
 
 #define IREENT_MAGIC	0x18041969