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[208.86.202.10]) by mx.google.com with ESMTPS id kv14si19783423pab.159.2014.08.17.21.37.12 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Sun, 17 Aug 2014 21:37:13 -0700 (PDT) Received-SPF: temperror (google.com: error in processing during lookup of pguenther@proofpoint.com: DNS timeout) client-ip=208.86.202.10; Authentication-Results: mx.google.com; spf=temperror (google.com: error in processing during lookup of pguenther@proofpoint.com: DNS timeout) smtp.mail=pguenther@proofpoint.com Received: from hq-cas02.corp.proofpoint.com (hq-cas02.corp.proofpoint.com [10.20.7.202]) by admin1010.us.proofpoint.com (8.14.5/8.14.5) with ESMTP id s7I4aw10007997 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NOT) for ; Sun, 17 Aug 2014 21:36:58 -0700 Received: from the-guenther.attlocal.net (76.253.0.176) by hq-cas02.corp.proofpoint.com (10.20.7.200) with Microsoft SMTP Server (TLS) id 14.2.347.0; Sun, 17 Aug 2014 21:36:58 -0700 Date: Sun, 17 Aug 2014 21:36:52 -0700 From: Philip Guenther X-X-Sender: guenther@morgaine.local To: David Gwynne Subject: the amd64/include/atomic.h part Message-ID: User-Agent: Alpine 2.11 (BSO 23 2013-08-11) MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" X-Originating-IP: [76.253.0.176] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.12.52,1.0.27,0.0.0000 definitions=2014-08-17_03:2014-08-15,2014-08-17,1970-01-01 signatures=0 X-Proofpoint-Spam-Details: rule=notspam policy=default score=0 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=7.0.1-1402240000 definitions=main-1408180062 Status: RO X-Status: A Content-Length: 4000 Lines: 159 Index: arch/amd64/include/atomic.h =================================================================== RCS file: /cvs/src/sys/arch/amd64/include/atomic.h,v retrieving revision 1.13 diff -u -p -r1.13 atomic.h --- arch/amd64/include/atomic.h 18 Jul 2014 10:40:14 -0000 1.13 +++ arch/amd64/include/atomic.h 18 Aug 2014 04:36:20 -0000 @@ -60,8 +60,7 @@ _atomic_cas_uint(volatile unsigned int * { __asm volatile(LOCK " cmpxchgl %2, %1" : "=a" (n), "=m" (*p) - : "r" (n), "a" (e), "m" (*p) - : "memory"); + : "r" (n), "a" (e), "m" (*p)); return (n); } @@ -72,8 +71,7 @@ _atomic_cas_ulong(volatile unsigned long { __asm volatile(LOCK " cmpxchgq %2, %1" : "=a" (n), "=m" (*p) - : "r" (n), "a" (e), "m" (*p) - : "memory"); + : "r" (n), "a" (e), "m" (*p)); return (n); } @@ -84,12 +82,128 @@ _atomic_cas_ptr(volatile void *p, void * { __asm volatile(LOCK " cmpxchgq %2, %1" : "=a" (n), "=m" (*(unsigned long *)p) - : "r" (n), "a" (e), "m" (*(unsigned long *)p) - : "memory"); + : "r" (n), "a" (e), "m" (*(unsigned long *)p)); return (n); } #define atomic_cas_ptr(_p, _e, _n) _atomic_cas_ptr((_p), (_e), (_n)) + +static inline void +_atomic_inc_int(volatile unsigned int *p) +{ + __asm volatile(LOCK " incl %0" + : "+m" (*p)); +} +#define atomic_inc_int(_p) _atomic_inc_int((_p)) + +static inline void +_atomic_inc_long(volatile unsigned long *p) +{ + __asm volatile(LOCK " incq %0" + : "+m" (*p)); +} +#define atomic_inc_long(_p) _atomic_inc_long((_p)) + +static inline void +_atomic_dec_int(volatile unsigned int *p) +{ + __asm volatile(LOCK " decl %0" + : "+m" (*p)); +} +#define atomic_dec_int(_p) _atomic_dec_int((_p)) + +static inline void +_atomic_dec_long(volatile unsigned long *p) +{ + __asm volatile(LOCK " decq %0" + : "+m" (*p)); +} +#define atomic_dec_long(_p) _atomic_dec_long((_p)) + +static inline void +_atomic_add_int(volatile unsigned int *p, unsigned int v) +{ + __asm volatile(LOCK " addl %1,%0" + : "+m" (*p) + : "a" (v)); +} +#define atomic_add_int(_p, _v) _atomic_add_int((_p), (_v)) + +static inline void +_atomic_add_long(volatile unsigned long *p, unsigned long v) +{ + __asm volatile(LOCK " addq %1,%0" + : "+m" (*p) + : "a" (v)); +} +#define atomic_add_long(_p, _v) _atomic_add_long((_p), (_v)) + +static inline void +_atomic_sub_int(volatile unsigned int *p, unsigned int v) +{ + __asm volatile(LOCK " subl %1,%0" + : "+m" (*p) + : "a" (v)); +} +#define atomic_sub_int(_p, _v) _atomic_sub_int((_p), (_v)) + +static inline void +_atomic_sub_long(volatile unsigned long *p, unsigned long v) +{ + __asm volatile(LOCK " subq %1,%0" + : "+m" (*p) + : "a" (v)); +} +#define atomic_sub_long(_p, _v) _atomic_sub_long((_p), (_v)) + + +static inline unsigned long +_atomic_add_int_nv(volatile unsigned int *p, unsigned int v) +{ + unsigned int rv = v; + + __asm volatile(LOCK " xaddl %0,%1" + : "+a" (rv), "+m" (*p)); + + return (rv + v); +} +#define atomic_add_int_nv(_p, _v) _atomic_add_int_nv((_p), (_v)) + +static inline unsigned long +_atomic_add_long_nv(volatile unsigned long *p, unsigned long v) +{ + unsigned long rv = v; + + __asm volatile(LOCK " xaddq %0,%1" + : "+a" (rv), "+m" (*p)); + + return (rv + v); +} +#define atomic_add_long_nv(_p, _v) _atomic_add_long_nv((_p), (_v)) + +static inline unsigned long +_atomic_sub_int_nv(volatile unsigned int *p, unsigned int v) +{ + unsigned int rv = 0 - v; + + __asm volatile(LOCK " xaddl %0,%1" + : "+a" (rv), "+m" (*p)); + + return (rv - v); +} +#define atomic_sub_int_nv(_p, _v) _atomic_sub_int_nv((_p), (_v)) + +static inline unsigned long +_atomic_sub_long_nv(volatile unsigned long *p, unsigned long v) +{ + unsigned long rv = 0 - v; + + __asm volatile(LOCK " xaddq %0,%1" + : "+a" (rv), "+m" (*p)); + + return (rv - v); +} +#define atomic_sub_long_nv(_p, _v) _atomic_sub_long_nv((_p), (_v)) static __inline u_int64_t x86_atomic_testset_u64(volatile u_int64_t *ptr, u_int64_t val)